Developing Integrated Solutions and Wet Cleans to Eliminate Tungsten Contact Attack in Sub 0x nm Nodes

2018 ◽  
Vol 282 ◽  
pp. 273-277
Author(s):  
Akshey Sehgal ◽  
Michael DeVre ◽  
Elango Balu
Keyword(s):  
Semiconductor Industry ◽  
High Volume ◽  
Metal Contact ◽  
Line Formation ◽  
New Materials ◽  
Metal Line ◽  
Dry Etch ◽  
Node Development

Having successfully developed high volume manufacturing (HVM) processes for the 0x nm node, the semiconductor industry is now engaged in developing the next advanced node. This 0xnm node development is being accomplished by a combination of shrinking 0x nm dimensions, introducing new materials and films and consequently new lithography, dry etch and wet clean processes for the new node. One of the major challenges is developing processes, including BEOL Cleans Steps, to successfully and reliably expose the MOL metal contact during the first metal line formation without degrading the contact itself. One such compatible method/clean is discussed in this study.

Stability of Co/Ni Silicide in Metal Contact Dry Etch

2004 ◽  
Vol 14 (8) ◽  
pp. 573-578
Author(s):  
Ohsung Song ◽  
Sungjin Beom ◽  
Dugjoong Kim
Keyword(s):  
Metal Contact ◽  
Dry Etch

3D Technology Applications Market Trends & Key Challenges

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000363-000400
Author(s):  
Thibault Buisson ◽  
Amandine Pizzagalli ◽  
Eric Mounier ◽  
Rozalia Beica
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
Semiconductor Industry ◽  
High Volume ◽  
Advanced Technology ◽  
Passive Component ◽  
Process Technology ◽  
3D Integration ◽  
3D Technology ◽  
Major Player

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging option, considered today the most advanced technology, that could enable various heterogeneous integration. Indeed such technology is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive component...) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that need to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with a multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

Increased High-Temperature Reliability and Package Hardening of Commercial Integrated Circuits (Through Die Extraction, Electroless Nickel/Gold Pad Reconditioning, and Ceramic Re-Assembly)

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000123-000128
Author(s):  
Erick M. Spory
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Value Added ◽  
Electroless Nickel ◽  
High Volume ◽  
Gold Plating ◽  
Global Circuit ◽  
Temperature Applications

There is an ever-increasing demand for electronics in higher temperature applications, both in variety and volume. In many cases, the actual integrated circuit within the plastic packaging can support operation at higher temperatures, although the packaging and connectivity is unable to do so. Ultimately, there still remains a significant gap in the volume demand required for high temperature integrated circuit lines to justify support of more expensive ceramic solutions by the original component manufacturer vs. the cheaper, high-volume PEM flows. Global Circuit Innovations, Inc. has developed a manufacturable, cost-effective solution to extract the integrated circuit from any plastic encapsulated device and subsequently re-package that device into an identical ceramic footprint, with the ability to maintain high-integrity connectivity to the device and enabling functionality for 1000's of hours at temperatures at 250C and beyond. This process represents a high-value added solution to provide high-temperature integrated circuits for a large spectrum of requirements: low-volume, quick-turn evaluation of integrated circuit prototyping, as well as medium to high-volume production needs for ongoing production needs. Although both die extraction and integrated circuit pad electroless nickel/gold plating have both been performed successfully for many years in the semiconductor industry, Global Circuit Innovations, Inc. has been able to combine the two in a reliable, volume manufacturing flow to satisfy many of the stringent requirements for high-temperature applications.

SHORT LOOP ELECTRICAL AND RELIABILITY LEARNING FOR THROUGH SILICON VIA (TSV)MID-WAFER FRONT-SIDE PROCESSES

2014 ◽  
Vol 2014 (1) ◽  
pp. 000794-000803 ◽  
Author(s):  
Victor Vartanian ◽  
Klaus Hummler ◽  
Steve Olson ◽  
Tyler Barbera ◽  
Kai-Hung Yu ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
High Volume ◽  
Front Side ◽  
Wafer Level ◽  
Metal Line ◽  
Through Silicon Via ◽  
Fully Integrated ◽  
Short Loop ◽  
Voltage Ramp ◽  
Reliability Assessments

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.

scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Commercial MEMS Case Studies: The Impact of Materials, Processes and Designs

2008 ◽  
Vol 1139 ◽  
Author(s):  
Jack Martin
Keyword(s):  
Case Studies ◽  
New Product ◽  
High Volume ◽  
New Materials ◽  
Case Study Approach ◽  
Product Planning ◽  
Study Approach ◽  
The Impact ◽  
New Devices

AbstractMinimizing risk is an important factor in new product planning because high volume breakthrough products require tens of millions of dollars to develop and bring to market. Sometimes risk can be minimized by following the IC model: build new devices on an existing process – just change the mask set. This approach obviously has limits. Adoption of new materials and processes greatly expands the horizon for “disruptive” products. This paper uses a case study approach to examine how changes in masks, materials and unit processes were used, and will continue to be used, to produce MEMS products for high volume applications.

Electron beam resist systems: A critical review of recent developments

1983 ◽  
Vol 41 ◽  
pp. 82-85
Author(s):  
M.P.C. Watts
Keyword(s):  
Confidence Limit ◽  
Semiconductor Industry ◽  
Critical Dimension ◽  
Optical Lithography ◽  
Direct Write ◽  
Beam Size ◽  
Resolution Limit ◽  
Recent Developments ◽  
Dry Etch ◽  
Process Compatibility

The aim of this paper is to critically review the latest commercial and scientific resist developments in the light of the needs of the semiconductor industry in direct write applications. These needs can be expressed as a set of usable ranges for sensitivity, resolution, and process compatibility, most notably dry etch resistance. The resist sensitivity needed for tolerable throughput varies from 0.5uCoul/cm2 to 20 uCoul/cm2 depending on the machine being used. Submicron resolution is now a necessity (0.1-1.0 um) because circuits with 1-2 um features are being made using optical lithography.The resolution limit of a resist is difficult to measure because resolution depends critically on the “image quality” (beam size/shape). Furthermore, for a given critical dimension to be used in a VLSI Si process, that dimension must be reproducible to within tight statistical limits, eg., for Hewlett-Packard's NMOS process the requirement is 1.5um lines, 1um spaces with a 3σ of +/− 0.25um (99.9% confidence limit). With these caveats, SEM's of resolution test paterns can be used as a guide to working resolution.

SiP: Bringing Ideas to High Volume Reality

2015 ◽  
Vol 2015 (S2) ◽  
pp. S1-S35
Author(s):  
Rich Rice
Keyword(s):  
Form Factor ◽  
Product Space ◽  
Semiconductor Industry ◽  
Electronic Markets ◽  
High Volume ◽  
Vast Number ◽  
Revenue Growth ◽  
Growth System ◽  
Market Needs

The semiconductor industry has entered a phase of accelerating integration, on both the corporate and product fronts. Companies must provide integrated solutions to end electronic markets to maintain their business channels and revenue growth. System-in-Package (SiP) provides an avenue for product designers to increase functionality while reducing form factor, which are absolute requirements for a vast number of applications particularly in the mobile product space. This presentation will cover the industry landscape, and highlight the key packaging technologies to be deployed in coming years to enable semiconductor and electronic companies meet evolving market needs.

Applicable Solvent Photoresist Strip Process for High-K/Metal Gate

2012 ◽  
Vol 187 ◽  
pp. 105-108
Author(s):  
Masayuki Wada ◽  
H. Takahashi ◽  
J. Snow ◽  
Rita Vos ◽  
P.W. Mertens ◽  
...  
Keyword(s):  
High Volume ◽  
Device Fabrication ◽  
New Materials ◽  
Metal Gate ◽  
Technology Innovations ◽  
Integration Schemes ◽  
High K ◽  
Wet Processing ◽  
Near Future ◽  
28 Nm

In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.

Etch Rate Study of Germanium, GaAs and InGaAs: A Challenge in Semiconductor Processing

2009 ◽  
Vol 145-146 ◽  
pp. 203-206 ◽  
Author(s):  
Sonja Sioncke ◽  
David P. Brunco ◽  
Marc Meuris ◽  
Olivier Uwamahoro ◽  
Jan Van Steenbergen ◽  
...  
Keyword(s):  
Etch Rate ◽  
Carrier Mobility ◽  
Semiconductor Industry ◽  
Semiconductor Material ◽  
New Materials ◽  
Semiconductor Processing ◽  
Moore’S Law ◽  
Rate Study ◽  
Chemical Solutions ◽  
Etch Rates

The Si transistor has dominated the semiconductor industry for decades. However, to fulfill the demands of Moore’s law, the Si transistor has been pushed to its physical limits. Introducing new materials with higher intrinsic carrier mobility is one way to solve this problem. Ge, GaAs and InGaAs are known for their high mobilities and are therefore suitable candidates for replacing Si as a channel material. However, introduction of new materials raises new issues. For Si processing, several steps such as cleaning, etching and stripping are based on wet treatments. The knowledge of etch rates of the semiconductor material is of great importance. In this paper, etch rates of Ge, GaAs and InGaAs in several chemical solutions are studied. A comparison of the etch rates is made between the materials.

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