Development of Substrates for Through Glass Vias

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000832-000845 ◽  
Author(s):  
Aric Shorey ◽  
Scott Pollard
Keyword(s):  
Material Properties ◽  
Glass Composition ◽  
Coefficient Of Thermal Expansion ◽  
Cost Effective ◽  
High Volume ◽  
Chemical Durability ◽  
Thin Glass ◽  
Wide Range ◽  
Challenges And Opportunities ◽  
Substantial Progress

Through-substrate vias are critical for 3DS-IC integration. The choice of glass as an interposer substrate, TGV, present some interesting challenges and opportunities, making glass a compelling alternative to silicon. There are two primary challenges to begin building a precision interposer in thin glass. The first is high quality thin glass wafers (300 mm OD, thickness 0.05 to 0.10 mm, warp and TTV of 30 μm and 1 μm respectively). The second challenge is developing a process capable of providing small (5–10 μm) precision vias in a cost-effective way. “Glass” represents a large class of materials with a wide range of material properties. The first step in developing TGV is to identify the most appropriate glass composition for the application, which furthermore defines important properties such as coefficient of thermal expansion (CTE) and other mechanical properties, chemical durability and electrical properties. The manufacturing process used to develop the glass has a significant impact on quality and manufacturability. Fusion formed glass provides a solution for high volume manufacturing supply in an as-formed, ultra-thin, pristine glass manufactured to tight tolerances, and avoids the issues associated with polishing or thinning. The supply of 50 μm to 100 μm as-formed ultra-thin glass wafers can compare very favorably in cost relative to polished or thinned glass as well as thinned silicon wafer. While there are many technologies that have demonstrated vias in glass, challenges relating to via size and pitch, wafer strength and reliability remain to be resolved. However, substantial progress has been made to meet these challenges. Specific characterization data from some of these processes to demonstrate vias on the order of 10 μm diameter with a 100 μm glass thickness in alternative glass materials will be presented.

scholarly journals Progress, Challenges and Opportunities in Divalent Transition Metal-Doped Cobalt Ferrites Nanoparticles Applications

2020 ◽  
Author(s):  
Oana Cadar ◽  
Thomas Dippong ◽  
Marin Senila ◽  
Erika-Andrea Levei
Keyword(s):  
Cost Effective ◽  
Synthesis Methods ◽  
Application Range ◽  
High Electrical Resistivity ◽  
Cobalt Ferrites ◽  
Wide Range ◽  
Challenges And Opportunities ◽  
Preparation Route ◽  
Metal Doped ◽  
New Applications

Engineered nanomaterials with tailored properties are highly required in a wide range of industrial fields. Consequently, the researches dedicated to the identification of new applications for existing materials and to the development of novel promising materials and cost effective, eco-friendly synthesis methods gained considerable attention in the last years. Cobalt ferrite is one of the nanomaterials with a wide application range due to its unique properties such as high electrical resistivity, negligible eddy current loss, moderate saturation magnetization, chemical and thermal stability, high Curie temperature and high mechanical hardness. Moreover, its structural, magnetic and electrical properties can be tailored by the selection of preparation route, chemical composition, dopant ions and thermal treatment. This chapter presents the recent applications of nanosized cobalt ferrites doped or co-doped with divalent transition ions such as Zn2+, Cu2+, Mn2+, Ni2+, Cd2+ obtained by various synthesis methods in ceramics, medicine, catalysis, electronics and communications.

Innovated Process Integration for Panel Size Glass Substrate Manufacturing for SiP Application

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001893-001917 ◽  
Author(s):  
Yu-Hua Chen ◽  
Yu-Chung Hsieh ◽  
Wei-Di Lin ◽  
Chun-Hsien Chien ◽  
Dyi-Chung Hu
Keyword(s):  
Line Width ◽  
Glass Substrate ◽  
Process Integration ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Unit Cost ◽  
High Volume ◽  
Thin Glass ◽  
Panel Size ◽  
Wafer Processing

Although Silicon interposer has good performance, however high cost is still the major issue and limits its high volume adoption. Therefore to decrease the assembly cost or develop low cost, high density interconnect interposer technology is the keys to enable 2.5D SiP integration. One possibility is to develop low cost interposer by adopting the alternative materials instead of Silicon. The glass, low CTE polymer material, ceramic, etc. may be included. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. Additionally, the two sided processing of the panel, the avoidance of Si wafer CMP processes further enable lower unit cost for the interposer Consequently, glass is an ideal interposer material due to its insulating property, large panel size availability, high modulus and ability to tailor CTE. In this paper, we successfully demonstrate manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel in 508mm×508mm panel size format and under the IC substrate manufacturing environment. Glass thickness of 100~300um could be processed through the IC substrate HVM line. The laser via in via or direct metallization technology could be selected for double side electrical connection. The copper line width/space of 8/8um was demonstrated by current substrate HVM line. By adopting advanced lithography process and material, line width/space less than 2/2um was achievable. TCT Reliability test without glass crack results will also be discussed.

scholarly journals Curved-crease origami face shields for infection control

PLoS ONE ◽  
2021 ◽  
Vol 16 (2) ◽  
pp. e0245737
Author(s):  
Aurimas Bukauskas ◽  
Antiopi Koronaki ◽  
Ting-Uei Lee ◽  
Daniel Ott ◽  
M. Wesam Al Asali ◽  
...  
Keyword(s):  
Infection Control ◽  
Parametric Design ◽  
Plastic Material ◽  
Cost Effective ◽  
High Volume ◽  
Middle Income ◽  
Wide Range ◽  
Global Demand ◽  
Production And Distribution ◽  
The Face

The COVID-19 pandemic has created enormous global demand for personal protective equipment (PPE). Face shields are an important component of PPE for front-line workers in the context of the COVID-19 pandemic, providing protection of the face from splashes and sprays of virus-containing fluids. Existing face shield designs and manufacturing procedures may not allow for production and distribution of face shields in sufficient volume to meet global demand, particularly in Low and Middle-Income countries. This paper presents a simple, fast, and cost-effective curved-crease origami technique for transforming flat sheets of flexible plastic material into face shields for infection control. It is further shown that the design could be produced using a variety of manufacturing methods, ranging from manual techniques to high-volume die-cutting and creasing. This demonstrates the potential for the design to be applied in a variety of contexts depending on available materials, manufacturing capabilities and labour. An easily implemented and flexible physical-digital parametric design methodology for rapidly exploring and refining variations on the design is presented, potentially allowing others to adapt the design to accommodate a wide range of ergonomic and protection requirements.

2D Color-Intensity Representation of Ultrasonic Thickness Gauge Measurements

2020 ◽  
pp. 1192-1198
Author(s):  
M.S. Mohammad ◽  
Tibebe Tesfaye ◽  
Kim Ki-Seong
Keyword(s):  
Cost Effective ◽  
The Other ◽  
Thickness Gauge ◽  
Color Intensity ◽  
Digital Readout ◽  
Flat Surfaces ◽  
Video Cameras ◽  
Wide Range ◽  
Cost Effective Alternative ◽  
Ultrasonic Thickness

Ultrasonic thickness gauges are easy to operate and reliable, and can be used to measure a wide range of thicknesses and inspect all engineering materials. Supplementing the simple ultrasonic thickness gauges that present results in either a digital readout or as an A-scan with systems that enable correlating the measured values to their positions on the inspected surface to produce a two-dimensional (2D) thickness representation can extend their benefits and provide a cost-effective alternative to expensive advanced C-scan machines. In previous work, the authors introduced a system for the positioning and mapping of the values measured by the ultrasonic thickness gauges and flaw detectors (Tesfaye et al. 2019). The system is an alternative to the systems that use mechanical scanners, encoders, and sophisticated UT machines. It used a camera to record the probe’s movement and a projected laser grid obtained by a laser pattern generator to locate the probe on the inspected surface. In this paper, a novel system is proposed to be applied to flat surfaces, in addition to overcoming the other limitations posed due to the use of the laser projection. The proposed system uses two video cameras, one to monitor the probe’s movement on the inspected surface and the other to capture the corresponding digital readout of the thickness gauge. The acquired images of the probe’s position and thickness gauge readout are processed to plot the measured data in a 2D color-coded map. The system is meant to be simpler and more effective than the previous development.

The Future of Plasma-Based Surface Engineering Techniques in Tribology (Keynote)

2005 ◽  
Author(s):  
Allan Matthews ◽  
Adrian Leyland
Keyword(s):  
Surface Engineering ◽  
Performance Enhancement ◽  
Bulk Material ◽  
Cost Savings ◽  
Cost Effective ◽  
Ceramic Coatings ◽  
Performance Improvements ◽  
Treatment Techniques ◽  
Wide Range ◽  
Macro Scale

Over the past twenty years or so, there have been major steps forward both in the understanding of tribological mechanisms and in the development of new coating and treatment techniques to better “engineer” surfaces to achieve reductions in wear and friction. Particularly in the coatings tribology field, improved techniques and theories which enable us to study and understand the mechanisms occurring at the “nano”, “micro” and “macro” scale have allowed considerable progress to be made in (for example) understanding contact mechanisms and the influence of “third bodies” [1–5]. Over the same period, we have seen the emergence of the discipline which we now call “Surface Engineering”, by which, ideally, a bulk material (the ‘substrate’) and a coating are combined in a way that provides a cost-effective performance enhancement of which neither would be capable without the presence of the other. It is probably fair to say that the emergence and recognition of Surface Engineering as a field in its own right has been driven largely by the availability of “plasma”-based coating and treatment processes, which can provide surface properties which were previously unachievable. In particular, plasma-assisted (PA) physical vapour deposition (PVD) techniques, allowing wear-resistant ceramic thin films such as titanium nitride (TiN) to be deposited on a wide range of industrial tooling, gave a step-change in industrial productivity and manufactured product quality, and caught the attention of engineers due to the remarkable cost savings and performance improvements obtained. Subsequently, so-called 2nd- and 3rd-generation ceramic coatings (with multilayered or nanocomposite structures) have recently been developed [6–9], to further extend tool performance — the objective typically being to increase coating hardness further, or extend hardness capabilities to higher temperatures.

scholarly journals Gamma models for estimating the odds ratio for a skewed biomarker measured in pools and subject to errors

Biostatistics ◽  
2019 ◽  
Author(s):  
Dane R Van Domelen ◽  
Emily M Mitchell ◽  
Neil J Perkins ◽  
Enrique F Schisterman ◽  
Amita K Manatunga ◽  
...  
Keyword(s):  
Odds Ratio ◽  
Adjusted Odds Ratio ◽  
Lower Cost ◽  
Cost Effective ◽  
Ratio Estimation ◽  
Statistical Efficiency ◽  
Function Model ◽  
Processing Error ◽  
Wide Range ◽  
Pooled Samples

SUMMARYMeasuring a biomarker in pooled samples from multiple cases or controls can lead to cost-effective estimation of a covariate-adjusted odds ratio, particularly for expensive assays. But pooled measurements may be affected by assay-related measurement error (ME) and/or pooling-related processing error (PE), which can induce bias if ignored. Building on recently developed methods for a normal biomarker subject to additive errors, we present two related estimators for a right-skewed biomarker subject to multiplicative errors: one based on logistic regression and the other based on a Gamma discriminant function model. Applied to a reproductive health dataset with a right-skewed cytokine measured in pools of size 1 and 2, both methods suggest no association with spontaneous abortion. The fitted models indicate little ME but fairly severe PE, the latter of which is much too large to ignore. Simulations mimicking these data with a non-unity odds ratio confirm validity of the estimators and illustrate how PE can detract from pooling-related gains in statistical efficiency. These methods address a key issue associated with the homogeneous pools study design and should facilitate valid odds ratio estimation at a lower cost in a wide range of scenarios.

scholarly journals A Slot-Die Technique for the Preparation of Continuous, High-Area, Chitosan-Based Thin Films

Polymers ◽  
2021 ◽  
Vol 13 (10) ◽  
pp. 1566
Author(s):  
Oliver J. Pemble ◽  
Maria Bardosova ◽  
Ian M. Povey ◽  
Martyn E. Pemble
Keyword(s):  
Thin Films ◽  
Mechanical Properties ◽  
High Volume ◽  
Mechanical Anisotropy ◽  
Diverse Range ◽  
Direction Parallel ◽  
High Area ◽  
Wide Range ◽  
Slot Die ◽  
Potential Applications

Chitosan-based films have a diverse range of potential applications but are currently limited in terms of commercial use due to a lack of methods specifically designed to produce thin films in high volumes. To address this limitation directly, hydrogels prepared from chitosan, chitosan-tetraethoxy silane, also known as tetraethyl orthosilicate (TEOS) and chitosan-glutaraldehyde have been used to prepare continuous thin films using a slot-die technique which is described in detail. By way of preliminary analysis of the resulting films for comparison purposes with films made by other methods, the mechanical strength of the films produced was assessed. It was found that as expected, the hybrid films made with TEOS and glutaraldehyde both show a higher yield strength than the films made with chitosan alone. In all cases, the mechanical properties of the films were found to compare very favorably with similar measurements reported in the literature. In order to assess the possible influence of the direction in which the hydrogel passes through the slot-die on the mechanical properties of the films, testing was performed on plain chitosan samples cut in a direction parallel to the direction of travel and perpendicular to this direction. It was found that there was no evidence of any mechanical anisotropy induced by the slot die process. The examples presented here serve to illustrate how the slot-die approach may be used to create high-volume, high-area chitosan-based films cheaply and rapidly. It is suggested that an approach of the type described here may facilitate the use of chitosan-based films for a wide range of important applications.

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

2021 ◽  
Vol 29 (5) ◽  
pp. 843-856
Author(s):  
Sriram Vangal ◽  
Somnath Paul ◽  
Steven Hsu ◽  
Amit Agarwal ◽  
Saurabh Kumar ◽  
...  
Keyword(s):  
Wide Range ◽  
Challenges And Opportunities ◽  
Many Core ◽  
Scaled Cmos
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