Development of Low RON,Diff, 12 kV, 4H-SiC GTOs For High-Power and High-Temperature Applications

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000149-000153 ◽  
Author(s):  
Lin Cheng ◽  
Anant K. Agarwal ◽  
Michael Oloughlin ◽  
Al Burk ◽  
Craig Capell ◽  
...  
Keyword(s):  
High Temperature ◽  
High Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
High Injection Level ◽  
Curve Tracer ◽  
Blocking Voltage ◽  
High Temperature Measurement ◽  
Forward Voltage Drop ◽  
Set Up

In this paper, we report our recently developed 1 × 1 cm2, 12 kV SiC GTOs with a very low differential on-resistance (RON,Diff) of 4 mΩ·cm2 with respect to the device active area at high injection level current of 100 A/cm2 or higher, which is more than a 40% reduction from our previously reported work. This significant reduction in the on-resistance was attributed to an improvement of carrier lifetime in the SiC bulk region. The SiC GTO was wire-bonded and attached to a high-voltage package before the high-temperature measurement. Forward characteristics of the device were then measured using a Tektronics 371 curve tracer from room temperature up to 400°C. Over the temperature range, the RON,Diff of the 4H-SiC GTO increased modestly from 4 mΩ·cm2 at 20°C to 4.7 mΩ·cm2 at 400°C, while the forward voltage drop at 100 A decreased slightly from 3.97 V at 20°C to 3.6 V at 400°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current was measured 0.66 μA at a VGK of 12 kV at 20°C.

Effect of Current-Spreading Layer Formed by Ion Implantation on the Electrical Properties of High-Voltage 4H-SiC p-Channel IGBTs

2014 ◽  
Vol 778-780 ◽  
pp. 1038-1041 ◽  
Author(s):  
Tadayoshi Deguchi ◽  
Shuji Katakami ◽  
Hiroyuki Fujisawa ◽  
Kensuke Takenaka ◽  
Hitoshi Ishimori ◽  
...  
Keyword(s):  
Ion Implantation ◽  
High Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Temperature Stability ◽  
Bipolar Transistors ◽  
Forward Voltage ◽  
Current Spreading ◽  
Blocking Voltage ◽  
Forward Voltage Drop

High-voltage SiC p-channel insulated-gate bipolar transistors (p-IGBT) utilizing current-spreading layer (CSL) formed by ion implantation are fabricated and their properties characterized. A high blocking voltage of 15 kV is achieved at room temperature by optimizing the JFET length. An ampere-class p-IGBT exhibited a low forward voltage drop of 8.5 V at 100 A/cm2 and a low differential specific on-resistance of 33 mΩ cm2 at 250 °C, while these values were high at room temperature. For further reduction of the forward voltage drop in the on-state and temperature stability, the temperature dependence of the JFET effect and carrier lifetime in p-IGBTs are investigated. Optimization of the JFET length using an epitaxial CSL, instead of applying ion implantation and lifetime enhancement, could lead to a further reduction of the forward voltage drop.

scholarly journals Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance Using Calibrated TCAD Model

2020 ◽  
Vol 1004 ◽  
pp. 911-916 ◽  
Author(s):  
Daniel Johannesson ◽  
Keijo Jacobs ◽  
Staffan Norrga ◽  
Anders Hallén ◽  
Muhammad Nawaz ◽  
...  
Keyword(s):  
High Voltage ◽  
High Power ◽  
Voltage Drop ◽  
Forward Voltage ◽  
Blocking Voltage ◽  
Wide Range ◽  
Forward Voltage Drop ◽  
Static Performance ◽  
Simulation Results ◽  
Ultra High Voltage

In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general high-power application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.

1.8 kV, 10 mOhm-cm2 4H-SiC JFETs

2006 ◽  
Vol 911 ◽  
Author(s):  
James D. Scofield ◽  
Sei-Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Husna Fatima ◽  
Anant Agarwal
Keyword(s):  
High Temperature ◽  
Elevated Temperature ◽  
High Voltage ◽  
Electron Mobility ◽  
Room Temperature ◽  
Negative Shift ◽  
Dc Characteristics ◽  
Blocking Voltage

AbstractFabrication and characteristics of high voltage, normally-on JFETs in 4H-SiC are presented. The devices were built on 5x1015 cm-3 doped, 12 μm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 10 m Ω-cm2 and a blocking voltage of 1.8 kV were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by a factor of 5 and a decrease in transconductance were observed at 300oC, when compared to the value at room temperature. This is due to a decrease in bulk electron mobility at elevated temperature. A slight negative shift in pinch-off voltage was also observed at 300oC. The devices demonstrated robust DC characteristics for temperatures up to 300oC, and stable high temperature inverter operation in a power DC-DC converter application, using these devices, is reported in this paper.

Development of High Temperature Lateral HV and LV JFETs in 4H-SiC

2008 ◽  
Vol 600-603 ◽  
pp. 1091-1094 ◽  
Author(s):  
Y. Zhang ◽  
Kuang Sheng ◽  
Ming Su ◽  
Jian Hui Zhao ◽  
Petre Alexandrov ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
High Voltage ◽  
Threshold Voltage ◽  
Electron Mobility ◽  
Room Temperature ◽  
Low Voltage ◽  
Voltage Drop ◽  
Vertical Channel ◽  
Numerical Prediction

A series of high voltage (HV) and low voltage (LV) lateral JFETs are successfully developed in 4H-SiC based on the vertical channel LJFET (VC-LJFET) device platform. Both room temperature and 300 oC characterizations are presented. The HV JFET shows a specific-on resistance of 12.8 mΩ·cm2 and is capable of conducting current larger than 3 A at room temperature. A threshold voltage drop of about 0.5 V for HV and LV JFETs is observed when temperature varies from room temperature to 300 oC. The measured increase of specific-on resistance with temperature due to a reduction of electron mobility agrees with the numerical prediction. The first demonstration of SiC power integrated circuits (PIC) is also reported, which shows 5 MHz switching at VDS of 200 V and on-state current of 0.4 A.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Comparison of the Forward Voltage Drop of Si and SiC High Voltage Diodes

2014 ◽  
Vol 64 (7) ◽  
pp. 223-236 ◽  
Author(s):  
T. Gachovska ◽  
J. L. Hudgins
Keyword(s):  
High Voltage ◽  
Voltage Drop ◽  
Forward Voltage ◽  
Forward Voltage Drop

Impact of Carrier Lifetime Enhancement Using High Temperature Oxidation on 15 kV 4H-SiC P-GTO Thyristor

2017 ◽  
Vol 897 ◽  
pp. 587-590 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Daniel J. Lichtenwalner ◽  
Edward van Brunt ◽  
Craig Capell ◽  
Michael J. O’Loughlin ◽  
...  
Keyword(s):  
High Temperature ◽  
Carrier Lifetime ◽  
Voltage Drop ◽  
Current Gain ◽  
Slight Reduction ◽  
Temperature Oxidation ◽  
Forward Voltage Drop ◽  
P Type ◽  
The Impact ◽  
Lifetime Enhancement

The impact of the lifetime enhancement process using high temperature thermal oxidation method on 4H-SiC P-GTOs was investigated. 15 kV 4H-SiC P-GTOs with 140 μm thick drift layers, with and without 1450°C lifetime enhancement oxidation (LEO) process, were compared. The LEO process increased the average carrier lifetime in p-type epi layer from 0.9 μs to 6.25 μs, and it was observed that the effectiveness of the lifetime enhancement process was very sensitive to the doping concentration. The device with the LEO process showed a significant reduction in forward voltage drop and a substantially lower holding current, as expected from the carrier lifetime measurements. However, a slight reduction in blocking capability was also observed from the devices treated with LEO process. The common emitter current gain (β) of the wide base test NPN BJT was approximately 10X higher for the wafer with LEO process.

Simulation Study for the Structural Cell Design Optimization of 15kV SiC p-Channel IGBTs

2019 ◽  
Vol 963 ◽  
pp. 666-669
Author(s):  
Xiao Li Tian ◽  
Ben Tan ◽  
Yun Bai ◽  
Ji Long Hao ◽  
Cheng Yue Yang ◽  
...  
Keyword(s):  
Numerical Simulations ◽  
Design Optimization ◽  
Simulation Study ◽  
Voltage Drop ◽  
Cell Design ◽  
Forward Voltage ◽  
Trade Off ◽  
Structural Cell ◽  
Blocking Voltage ◽  
Forward Voltage Drop

In this paper, the structural cell design optimization of 15kV 4H-SiC p-channel IGBT is performed. The effects of the parameters of JFET region on the blocking voltage and the forward characteristics are analyzed by numerical simulations. The results indicate that the JFET width and JFET region concentration have an important effect on the performance of IGBTs. Based on the simulation structure in this paper, the optimum JFET width is 10μm, and the optimum JFET concentration is 7×1015cm−3. Meanwhile, they should be carefully designed to achieve the best trade-off between the blocking voltage and the forward voltage drop.

13-kV, 20-A 4H-SiC PiN Diodes for Power System Applications

2014 ◽  
Vol 778-780 ◽  
pp. 855-858 ◽  
Author(s):  
Dai Okamoto ◽  
Yasunori Tanaka ◽  
Tomonori Mizushima ◽  
Mitsuru Yoshikawa ◽  
Hiroyuki Fujisawa ◽  
...  
Keyword(s):  
Power System ◽  
High Voltage ◽  
Light Emission ◽  
Voltage Drop ◽  
High Current ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Current Switching ◽  
Forward Voltage Drop

We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (RonAactive) of 12 mW·cm2. The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.

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