Cost effective Precision 3D Glass Microfabrication for Electronic Packaging

2011 ◽  
Vol 2011 (1) ◽  
pp. 000199-000201
Author(s):  
Jeb H. Flemming ◽  
Kevin Dunn ◽  
James Gouker ◽  
Carrie Schmidt ◽  
Colin Buckley
Keyword(s):  
Glass Ceramic ◽  
Cost Effective ◽  
Electrical Performance ◽  
Sensitive Material ◽  
Aspect Ratios ◽  
3D Ics ◽  
Simple Processing ◽  
Micron Diameter ◽  
On Chip ◽  
Processing Steps

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; (1) electrical leakage and (2) the lack of improved electrical performance beyond 16nm. As a result, the industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost. In this extended abstract, 3D Glass Solutions, a division of Life BioScience, Inc., presents our efforts in glass interposer microfabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. 3D Glass Solution’s APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitch, in 125 micron thick APEX™ Glass ceramic. This extended abstract covers (1) on our efforts producing high aspect ratio TGVs in ultra thin (75–250 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.

Cost Effective Production of Glass Interposers for 3D ICs Using APEX(TM) Glass Ceramic

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001269-001290
Author(s):  
Jeb H. Flemming ◽  
Kevin Dunn ◽  
James Gouker ◽  
Carrie Schmidt
Keyword(s):  
Glass Ceramic ◽  
Cost Effective ◽  
Electrical Performance ◽  
Sensitive Material ◽  
Aspect Ratios ◽  
3D Ics ◽  
Simple Processing ◽  
Micron Diameter ◽  
On Chip ◽  
Processing Steps

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; electrical leakage and lack of improved electrical performance beyond 16nm. As a result, industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost. In this talk, we will present on our efforts in glass interposers fabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. Life MicroFab's APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitchs, in 125 micron thick APEX™ Glass ceramic. We will present (1) on our efforts producing high aspect ratio TGVs in thin (500-250 micron) and ultra thin (250-75 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.

Cost effective 3D Glass Microfabrication for Advanced Packaging Applications

2012 ◽  
Vol 2012 (1) ◽  
pp. 000781-000784
Author(s):  
Jeb H. Flemming ◽  
Kevin Dunn ◽  
James Gouker ◽  
Carrie Schmidt ◽  
Roger Cook
Keyword(s):  
Laser Ablation ◽  
Mechanical Strength ◽  
Glass Ceramic ◽  
Low Cost ◽  
Cost Effective ◽  
Consumer Electronics ◽  
Wet Etching ◽  
Ic Packaging ◽  
Advanced Packaging ◽  
Micron Diameter

Interposer technologies are gathering more importance in IC packaging as the industry continues miniaturization trends in microfabrication nodes and IC packaging to meet design and utility needs in consumer electronics. Furthermore, IC packaging is widely seen as a method to prolong Moore's law. Historically, silicon has been the material of interest for interposer materials given its prevalence in IC production, but it presents many technical and costs hurdles. In contrast, glass interposer technology presents a low cost alternative, yet attempts at producing advanced through glass vias (TGVs) arrays using traditional methods, such as laser ablation, have inherent process flaws, such as reduced interposer mechanical strength and debris sputtering among others. In this extended abstract we present 3D Glass Solutions' efforts in using our proprietary APEX™ Glass ceramic to create various interposer technologies. This extended abstract will present on the production of large arrays of 10 micron diameter TGVs, with 20 micron center-to-center pitch, in 100 micron thick APEX™ Glass ceramic and the comparisons of wet etching of APEX™ Glass vs. laser ablation.

scholarly journals 3D printed microfluidic lab-on-a-chip device for fiber-based dual beam optical manipulation

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Haoran Wang ◽  
Anton Enders ◽  
John-Alexander Preuss ◽  
Janina Bahnemann ◽  
Alexander Heisterkamp ◽  
...  
Keyword(s):  
Optical Fibers ◽  
Single Cells ◽  
Lab On A Chip ◽  
Cost Effective ◽  
Optical Manipulation ◽  
Hydrodynamic Focusing ◽  
Trapping Region ◽  
Dual Beam ◽  
3D Printed ◽  
On Chip

Abstract3D printing of microfluidic lab-on-a-chip devices enables rapid prototyping of robust and complex structures. In this work, we designed and fabricated a 3D printed lab-on-a-chip device for fiber-based dual beam optical manipulation. The final 3D printed chip offers three key features, such as (1) an optimized fiber channel design for precise alignment of optical fibers, (2) an optically clear window to visualize the trapping region, and (3) a sample channel which facilitates hydrodynamic focusing of samples. A square zig–zag structure incorporated in the sample channel increases the number of particles at the trapping site and focuses the cells and particles during experiments when operating the chip at low Reynolds number. To evaluate the performance of the device for optical manipulation, we implemented on-chip, fiber-based optical trapping of different-sized microscopic particles and performed trap stiffness measurements. In addition, optical stretching of MCF-7 cells was successfully accomplished for the purpose of studying the effects of a cytochalasin metabolite, pyrichalasin H, on cell elasticity. We observed distinct changes in the deformability of single cells treated with pyrichalasin H compared to untreated cells. These results demonstrate that 3D printed microfluidic lab-on-a-chip devices offer a cost-effective and customizable platform for applications in optical manipulation.

Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

2015 ◽  
Author(s):  
Tiantao Lu ◽  
Ankur Srivastava
Keyword(s):  
Mechanical Stress ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Thermal Reliability ◽  
Conduction Path ◽  
Placement Problem ◽  
Thermal Profile ◽  
3D Ic ◽  
3D Ics ◽  
Simulation Based

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

Development of All-Plastic Microvalve Array for Multiplexed Immunoassay

2014 ◽  
Author(s):  
Shancy Augustine ◽  
Pan Gu ◽  
Xiangjun Zheng ◽  
Toshikazu Nishida ◽  
Z. Hugh Fan
Keyword(s):  
Large Scale ◽  
Low Cost ◽  
Simultaneous Detection ◽  
Cost Effective ◽  
Negative Control ◽  
Sensitive Material ◽  
Detection Scheme ◽  
Power Battery ◽  
Multiple Analytes ◽  
Multiplexed Immunoassay

There is a need for low-cost immunoassays that measure the presence and concentration of multiple harmful agents in one device. Currently, comparable immunoassays employ a one-analyte-per-test format that is time consuming and not cost effective for the requirement of detecting multiple analytes in a single sample. For instance, if a spectrum of harmful agents, including E. coli O157, cholera toxin, and Salmonella typhimurium, should be simultaneously monitored in foods and drinking water, then a one-analyte-per-test would be inefficient. This work demonstrates a platform capable of simultaneous detection of multiple analytes in a single, low-cost, microvalve array-enabled multiplexed immunoassay. This multiplexed immunoassay platform is demonstrated in a prototype COC (cyclic olefin copolymer) device with a 2×3 array in which 6 analytes can be detected simultaneously. In order to contain and regulate the flow of reagents in the multichannel device, an array of microfluidic valves actuated by a thermally expandable material and microfabricated resistors have been developed to direct the flow to the necessary assay sites. The microvalve-based immunoassay is shown to be reliable, easy to operate, and compatible with large-scale integration. The all-plastic microvalves use paraffin wax as the thermally sensitive material which drastically reduces power consumption by latching upon closing so that pulsed power is required only to close and latch the microvalve until it is necessary to re-open the valve. The multiplexed detection scheme has been demonstrated by using three proteins, C reactive protein (CRP) and transferrin, both of which are biomarkers associated with traumatic brain injury (TBI) as well as bovine serum albumin (BSA) as the negative control. Since there are no external bulky pneumatic accessories required to operate/latch the microvalves in the device, this compact, thermally actuated and latching microvalve-enabled multiplexed immunoassay has the potential to realize a portable, low power, battery operated microfluidic device for biological assays.

Manufacturing Metamaterials Using Synchrotron Lithography

2010 ◽  
Vol 75 ◽  
pp. 230-239
Author(s):  
Herbert O. Moser ◽  
Linke Jian ◽  
Shenbaga M.P. Kalaiselvi ◽  
Selven Virasawmy ◽  
Sivakumar M. Maniam ◽  
...  
Keyword(s):  
Electromagnetic Waves ◽  
Cost Effective ◽  
Pattern Generation ◽  
Geometrical Parameters ◽  
X Ray ◽  
Spectral Bands ◽  
Left Handed ◽  
Aspect Ratios ◽  
Multi Level ◽  
Primary Pattern

The function of metamaterials relies on their resonant response to electromagnetic waves in characteristic spectral bands. To make metamaterials homogeneous, the size of the basic resonant element should be less than 10% of the wavelength. For the THz range up to the visible, structure details of 50 nm to 30 μm are required as are high aspect ratios, tall heights, and large areas. For such specifications, lithography, in particular, synchrotron radiation deep X-ray lithography, is the method of choice. X-ray masks are made via primary pattern generation by means of electron or laser writing. Several different X-ray masks and accurate mask-substrate alignment are necessary for architectures requiring multi-level lithography. Lithography is commonly followed by electroplating of metallic replica. The process can also yield mould inserts for cost-effective manufacture by plastic moulding. We made metamaterials based on rod-split-rings, split-cylinders, S-string bi-layer chips, and S-string meta-foils. Left-handed resonance bands range from 2.4 to 216 THz. Latest is the all-metal self-supported flexible meta-foil with pass-bands of 45% up to 70% transmission at 3.4 to 4.5 THz depending on geometrical parameters.

scholarly journals Recent Advances in Hearing Aid Technology-A Review

2021 ◽  
Vol 9 (VI) ◽  
pp. 3427-3429
Author(s):  
Animita Das
Keyword(s):  
Hearing Aids ◽  
Hearing Aid ◽  
Cost Effective ◽  
System On Chip ◽  
Audio Signals ◽  
Technology System ◽  
The People ◽  
Chip Technology ◽  
On Chip ◽  
System 1

Hearing aids are electroacoustic gadgets commonly worn in or behind the ear and are intended to enhance the speech Nowadays hearing aids support various application unlike the traditional ones such that it can act like headphones streaming audio signals from internet-enabled devices connected wirelessly via Bluetooth. This paper aims to review the various advancements in the hearing aid technology. System on chip technology of the microcontroller have been used in various studies to develop and design an effective hearing assistant device and help the people with hearing impairment to lead a normal life. Ten articles have been reviewed for the study and it can be concluded that IoT is the future for an efficient, cost effective hearing assistive system [1]

scholarly journals Saline collection media and an extraction free workflow enables massively scalable, highly sensitive, and cost-effective SARS-CoV-2 testing

2020 ◽  
Author(s):  
Yan Wei Lim ◽  
Nicole Leonetti ◽  
Aakash Amin ◽  
Henrique Machado ◽  
Natasha Bonilla ◽  
...  
Keyword(s):  
Supply Chain ◽  
Sensitivity And Specificity ◽  
Limit Of Detection ◽  
Rna Extraction ◽  
Cost Effective ◽  
Scaling Up ◽  
Consumption Patterns ◽  
Highly Sensitive ◽  
Processing Steps

Abstract The challenges in scaling up SARS-CoV-2 testing capacity include shortages in the supply chain for consumables and reagents. Improvements in consumption patterns can be obtained through removal of key processing steps, including RNA extraction. Here, we present a scalable and validated extraction-free method for the detection of SARS-CoV-2 from swab specimens in saline, with a limit of detection at 1,000 GCE/mL and a sensitivity and specificity of 100%.

Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

2014 ◽  
pp. 399-419
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Internal Communication ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Delay Variations ◽  
On Chip

In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

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