Managing Voids in Underfill Process with 5-micron Gap Under Large Die

2012 ◽  
Vol 2012 (1) ◽  
pp. 000376-000383
Author(s):  
Hanzhuang Liang ◽  
Nordson Asymtek
Keyword(s):  
Flip Chip ◽  
Substrate Surface ◽  
Microelectronic Packaging ◽  
Flip Chips ◽  
Indium Bumps ◽  
Packaging Industry ◽  
Complex Features ◽  
Capillary Fluid ◽  
Near Future ◽  
Careful Design

Microelectronic packaging is continuously becoming smaller and denser, thus allowing for more functionalities and smaller devices including portable products. Flip-chip among other technologies continues to enable such trends. In fact denser arrays such as copper pillars or micro bumps of various metallurgies seem to be the technology of choice for the near future electronic interconnect. A technique is reviewed for successfully underfilling a 3cm2 Indium Phosphide flip-chip die mounted on a silicon substrate with 5 microns gap and large number of I/O (about 0.3 million indium bumps) connected in daisy chains. The method that resulted in a void-free underfill consisted of line dispensing along one side of the die such that the flow of the capillary fluid was normal to the direction of the daisy chains. For dot-dispense, substrate surface treatment and more careful design of dispense sequence helped to reduce voids. This study was compared to a manual dot-dispense technique that was unable to meet production throughput requirement, accuracy, repeatability and void-free. Achievement of void-free automated underfill into a 5-micron gap with complex features underneath a large flip chips will encourage today's microelectronic packaging industry to meet the challenges of smaller and denser components.

Precise underfill dispense in high-throughput chip-on-wafer packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Hanzhuang Liang
Keyword(s):  
Key Words ◽  
High Throughput ◽  
Cost Reduction ◽  
Flip Chip ◽  
Microelectronic Packaging ◽  
Portable Devices ◽  
Wafer Level ◽  
Flip Chips ◽  
Wafer Level Packaging ◽  
One Year

In today's microelectronic packaging, components are continuously designed smaller and assembled more densely to allow more functions to fit into compact portable devices. To enable this trend, more manufacturers are using flip chips that have more I/O's and smaller bumps sizes. This has introduced underfill dispensing that fills the gap between the flip chip and the substrate with polymer epoxy to help reduce thermal and mechanical stress at the bonding interface. In device packaging, the demands for cost reduction and miniaturization encourage the use of wafer-level packaging, such as the chip-on-wafer process. As a result, the challenges to this process have grown exponentially, and so have the challenges to underfill dispensing. For example, to package a device with a chip-last process, the keep-out-zone (KOZ) for underfill epoxy placement to nearby components is shrinking, e.g. from 700um to 300–500um within one year. A high-precision, high-throughput underfill dispensing process has been developed to conquer these challenges. This underfill process is being used in production for chip-on-wafer packaging. In one example, underfill must be dispensed within KOZ 300–500um at UPH 4000. New equipment and new dispensing techniques are under development to further push the limit on higher throughput and precision. Key words: underfill, dispense, microelectronic packaging, device packaging, wafer-level packaging, chip-on-wafer, chip-last, keep-out-zone, precision, throughput

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Surface Energy and Wettability Study of Flip Chip Packaging Materials

2011 ◽  
Vol 2011 (1) ◽  
pp. 000961-000970
Author(s):  
Jinlin Wang
Keyword(s):  
Surface Energy ◽  
Flip Chip ◽  
Substrate Surface ◽  
Solid Surfaces ◽  
Energy Calculation ◽  
Assembly Process ◽  
Flip Chip Packaging ◽  
Materials Used ◽  
Lead Free Solders ◽  
Ic Package

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.

Managing Voids in Adhesives for Medical Devices

2014 ◽  
Vol 2014 (1) ◽  
pp. 000567-000571
Author(s):  
M. Ruales ◽  
J. Merced ◽  
R. Ramos
Keyword(s):  
Medical Devices ◽  
Adhesive Layer ◽  
Microelectronic Packaging ◽  
Void Content ◽  
Curing Process ◽  
Curing Time ◽  
Optimal Process ◽  
Thermal Transfer ◽  
Device Reliability ◽  
Packaging Industry

Void content within the adhesive layer dispensed over the connector module in neuromodulation devices is critical. Voids can affect the thermal transfer, bond strength, and stress decoupling of the adhesive, which can eventually lead to degraded device reliability. The effects of voids are investigated for a silicone based adhesive used in these medical devices. There are many challenges associated with the curing process that this adhesive undergoes which drive the need for unique and specific testing to determine optimal process settings. The parameters evaluated included curing time, temperature, thickness, and relative humidity. Reduction in void content was linked with mechanical properties including hardness and tensile strength. Achievement of void free medical adhesives will encourage today's microelectronic packaging industry to meet the challenges of smaller and denser medical devices.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000548-000553 ◽  
Author(s):  
Fuliang Le ◽  
S. W. Ricky Lee ◽  
Jingshen Wu ◽  
Matthew M. F. Yuen
Keyword(s):  
Flip Chip ◽  
Through Silicon Vias ◽  
Flip Chips ◽  
Solder Bumps ◽  
Die Stacking ◽  
Chip Carrier ◽  
On Chip ◽  
Silicon Vias ◽  
3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

Reliability of Underfill-Encapsulated Flip-Chips With Heat Spreaders

1998 ◽  
Vol 120 (4) ◽  
pp. 322-327 ◽  
Author(s):  
H. Doi ◽  
K. Kawano ◽  
A. Yasukawa ◽  
T. Sato
Keyword(s):  
Mechanical Properties ◽  
Fatigue Life ◽  
Thermal Cycling ◽  
Failure Mode ◽  
Flip Chip ◽  
Solder Joints ◽  
Alumina Substrate ◽  
Heat Spreader ◽  
Flip Chips ◽  
Heat Spreaders

The effect of a heat spreader on the life of the solder joints for underfill-encapsulated, flip-chip packages is investigated through stress analyses and thermal cycling tests. An underfill with suitable mechanical properties is found to be able to prolong the fatigue life of the solder joints even in a package with a heat spreader and an alumina substrate. The delamination of the underfill from the chip is revealed as another critical failure mode for which the shape of the underfill fillet has a large effect.

Thermal Control of Interfaces for Microelectronic Packaging

1998 ◽  
Vol 515 ◽  
Author(s):  
E. E. Marotta ◽  
B. Hana
Keyword(s):  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Thermal Stresses ◽  
Experimental Studies ◽  
Thermal Control ◽  
Thermal Contact Conductance ◽  
Microelectronic Packaging ◽  
Chip Technology ◽  
Operating Temperatures

ABSTRACTThe continuous miniaturization of electronic devices places an ever-increasing importance on the thermal management of electronic systems and its subcomponents. The increased power densities and heat generation, due to the miniaturization of the device line features, may lead to higher operating temperatures and greater warpage between the silicon device and its organic carrier. The higher operating temperature may result from the degradation of the overall thermal performance. These additive effects will also lead to an increasing number of thermally induced failures, which will be further magnified when future microelectronic packaging incorporates flip-chip technology.The higher operating temperatures within microelectronic systems result from inadequate dissipation of the heat generated, while the warpage effect is caused by the mismatch between the thermal coefficients of expansion (ICE) induced by thermal stresses. Often these high temperatures result from the thermal resistance between subcomponents, such as between the contacting surfaces of laminated printed circuit boards, device/epoxy cement and heat spreader (i.e., finned heat sink or heat pipe), and any other metallic or non-metallic interstitial material employed between contacting interfaces.Published experimental data of potential coatings, adhesives, and elastomeric gaskets is presented that can improve the thermal contact conductance of contacting surfaces within microelectronic systems. In addition, recommendations for future analytical and experimental studies of the mnechanistic principles, which control thermal performance of interstitial materials, are discussed for non-uniform pressure distribution.

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