Finite element analysis of lidded flip-chip packages: A study on the impact of thermal interface material compressibility and stress-free conditions on modeling predictions

2015 ◽  
Vol 2015 (1) ◽  
pp. 000151-000156
Author(s):  
Tuhin Sinha
Keyword(s):  
Flip Chip ◽  
Image Correlation ◽  
Thermal Interface Material ◽  
Element Analysis ◽  
Thermal Interface ◽  
Strong Function ◽  
Linear Elastic ◽  
Fea Modeling ◽  
Predicted Values ◽  
The Impact

In this paper, we present the effects of assumptions made about the constitutive behavior of a cured, silicone gel type thermal interface material (TIM) and the package stress-free conditions on FEA modeling predictions. The focus will be on the deformations (or warpage) predicted by the models for lidded flip-chip packages. It is critical for such warpage predictions to be close to experimental measurements for accurate projection of mechanical stresses and strains in a package. Digital Image Correlation (DIC) warpage measurements on flip-chip modules are compared against the predicted values and the impact of above-mentioned assumptions will be discussed. It will be shown that the TIM mechanical and thereby, thermal degradation is a strong function of the TIM compressibility and stress-free condition assumptions. Bounds of non-linear elastic modeling technique for the TIM and guidelines for conducting numerical analysis for lidded flip-chip packages will be provided.

Novel Process Techniques to Reduce Voids in Solder Thermal Interface Materials Used for Flip-Chip Package Applications

2005 ◽  
Author(s):  
M. Montano ◽  
J. Garcia ◽  
W. Shi ◽  
M. T. Reiter ◽  
U. Vadakkan ◽  
...  
Keyword(s):  
Process Parameters ◽  
Thermal Performance ◽  
Flip Chip ◽  
Technical Conference ◽  
Thermal Interface Material ◽  
Electronic Systems ◽  
Thermal Interface ◽  
Cure Time ◽  
Materials Used ◽  
The Impact

In the present study, the thermal performance of flip chip electronics packages was evaluated by characterizing the amount of voiding present in the Solder Thermal Interface Material (STIM) which is placed between the die and Integrated Heat Spreader (IHS). The study found that the thermal resistance, Rjc (resistance between the Si die and IHS), is dependent upon the amount of voiding present as well as the location of the voiding in the STIM. The study also described the techniques to reduce the STIM voids in flip chip packages and identified the key process parameters to improve the thermal performance. The process parameters varied in this study consisted of STIM thickness, dwell time and temperature, flux weight, and many others. A detailed DOE and statistical analysis were carried out to determine the impact of the parameters mentioned above toward reducing the quantity of voids in the STIM. The analysis showed that for the packages under consideration, the primary process parameters that affect the STIM voiding are cure time, flux weight and TIM thickness.   This paper was also originally published as part of the Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems.

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

Hygro-Thermo-Mechanical Reliability Assessment of a Thermal Interface Material for a Ball Grid Array Package Assembly

2010 ◽  
Vol 132 (2) ◽  
Author(s):  
Xi Liu ◽  
Jiantao Zheng ◽  
Suresh K. Sitaraman
Keyword(s):  
Element Model ◽  
Moisture Diffusivity ◽  
Polymer Materials ◽  
Image Correlation ◽  
Thermal Interface Material ◽  
Effect Of Temperature ◽  
Normal Strain ◽  
Thermal Interface ◽  
Moisture Expansion ◽  
Wide Range

The thermal efficacy of thermal interface material (TIM) is highly dependent on its ability to adhere to the surfaces of interest. Any delamination of the TIM from the die or the lid will increase the local thermal resistance and, thus, will reduce the overall effectiveness of the TIM. Although significant amount of work has been done on understanding the thermal and moisture effects of various polymer materials used in microelectronic package assemblies, very limited work has been done to study the effect of temperature and moisture on TIM delamination. In this paper, a sequential hygro-thermal-mechanical finite-element model has been developed to mimic the loadsteps associated with package assembly as well as moisture soaking under 85°C/85RH over 500 h. The predictions from the models have been validated with a wide range of experimental data including laser Moiré data for thermomechanical loading and digital image correlation data for hygro-thermo-mechanical loading. Weight gain and coordinate-measurement machine have been used to characterize moisture diffusivity and moisture expansion coefficient of various polymer materials in the package assembly. The developed models show the evolution of normal strain in TIM during various loadsteps and provide important insight into the potential for TIM delamination under package assembly process and moisture soaking. Thus, the models can be used for developing various designs and process steps for reducing the chances for TIM delamination.

Precise, high throughput dispensing of thermal interface material in BGA packaging applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001391-001412
Author(s):  
Hanzhuang Liang ◽  
Linh Rolland
Keyword(s):  
High Throughput ◽  
Flip Chip ◽  
Consumer Electronics ◽  
Thermal Interface Material ◽  
Production Lines ◽  
Heat Spreader ◽  
Heavy Load ◽  
Thermal Interface ◽  
Wide Range ◽  
Complicated Geometries

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

Measurement of Local Residual Stress of a Flip Chip Structure Using a Stress Sensing Chip

2005 ◽  
Author(s):  
Nobuki Ueta ◽  
Hideo Miura
Keyword(s):  
Residual Stress ◽  
Polycrystalline Silicon ◽  
Flip Chip ◽  
Sensor Chip ◽  
Element Analysis ◽  
Strong Function ◽  
Chip Technology ◽  
Stress Sensing ◽  
Periodic Stress ◽  
Polycrystalline Silicon Films

Local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length. Each strain gauge was made of polycrystalline silicon films deposited on a silicon wafer. The periodic stress distribution was measured at a surface of the sensor chip between two bumps. Five gauges were aligned at a interval of 20-μm between the bumps. When the thickness of the chip was less than 200 μm, the amplitude of the stress increased drastically, as was predicted by a finite element analysis. The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 μm. The amplitude of the stress is a strong function of the thickness of a silicon chip and the intervals of the bumps.

Optimization of a Flux-Less Metal Thermal Interface Material by Reflow in a Vacuum Furnace

2011 ◽  
Vol 2011 (1) ◽  
pp. 000929-000937
Author(s):  
Pierino I Zappella ◽  
Paul W Barnes ◽  
David Muhs ◽  
Bruce Wilson
Keyword(s):  
Flip Chip ◽  
Pure Metal ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Vacuum Furnace ◽  
Acceptance Criteria ◽  
Specific Sequence ◽  
Thermal Interface ◽  
Series Of Experiments ◽  
Initial Objective

This paper describes the work performed with a pure metal thermal interface material (TIM) for the sole purpose to improve the transfer of heat from the die to the metal cover case. A flux-less reflow process is employed in order to reflow the indium TIM material. This operation is performed in a vacuum furnace utilizing heat, vacuum, and pressure in a specific sequence in order to wet the metal lid and the backside of the flip chip die. The initial objective was to demonstrate minimal voiding of the TIM and subsequently limited flow out of molten solder from and along the sides of the die. A series of experiments were employed where acceptance criteria is evaluated by a) X-Ray, b) scanning acoustical microscopy (SAM), and c) cross-section. Acceptance criteria consists of 1) indium wetting of both lid to indium interface and indium to silicon interface die, 2) indium bond line (BLT) thickness, 3) lid tilt, and 4) lid shear strength. Acceptance is determined after a subsequent 4X ball grid array (BGA) reflow in a conventional belt reflow furnace with minimal voiding, no popcorn or blistering of the laminate substrate, and TIM thickness and solder flow out at sides of the die within the acceptable limits of the above mentioned criteria.

The Span Mitigation Analysis With Use of Advanced FEA Modeling Techniques

2011 ◽  
Author(s):  
James Wang ◽  
Ranil Banneyake ◽  
Shawn Huang ◽  
Paul Jukes ◽  
Ayman Eltaher
Keyword(s):  
Element Analysis ◽  
Upheaval Buckling ◽  
Fea Modeling ◽  
Significant Damage ◽  
Static And Dynamic Loads ◽  
The Cost ◽  
Mitigation Methods ◽  
And Control ◽  
The Impact ◽  
Cost Factors

Spans occur when a pipeline is laid on a rough undulating seabed or when upheaval buckling occurs due to constrained thermal expansion. This not only results in static and dynamic loads on the flowline at the span section, but also generates vortex induce vibration (VIV) which can lead a fatigue issue. The phenomenon, if not predicted and control properly, will result in significant damage to the pipeline integrity, leading to expensive remediation and intervention works. There are various span mitigation methods in use for both over stressing and fatigue concerns. The mitigation methods, if not analyzed properly, may result in much unnecessary work or generate more problems or concerns in the future. The mitigation analysis can become very challenging due to many restrictions in the field such as the minimum and maximum heights or lift of mechanical supports or grout bags, and bearing capacity vs. cost of supports. The cost of different mitigation methods and their interactions are the other considerations along with the installation tolerances, challenges associated with the water depth and uncertainties in seabed properties. This paper describes the latest developments in use of finite element analysis to investigate associate mitigation solutions given the governing practical limitations and cost factors. The ULS and fatigue lift criteria are used as the guidelines. The methods presented within this paper are applicable for various span conditions. Conclusions are then drawn to the impact of these various scenarios so that the pipeline integrity can be assured with confidence.

Effects of Thermal Lids Gold Plating Thickness on Thermal Interface Reliability for Flip Chip Packaging

2007 ◽  
Author(s):  
Chin Hock Toh ◽  
Arun Raman ◽  
Thomas Fitzgerald ◽  
Madhuri Narkhede ◽  
Alfred A. La Mar ◽  
...  
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Thermal Interface Material ◽  
Thermal Impedance ◽  
Thermal Reliability ◽  
Gold Plating ◽  
Thermal Interface ◽  
Density Values ◽  
Flip Chip Packaging

This paper summarizes the intermetallic compounds (IMC) formation at the interface between thermal interface material (TIM) and nickel/gold plated integrated heat spreader (IHS) at varying Au thickness, and its impact on thermal reliability. Indium solders due to their high thermal conductivity are commonly used as the TIM to dissipate heat from silicon die to the thermal lids for new generation microprocessors with higher operating die temperatures. Indium solders readily wet the Au plating on thermal lids to form IMC during soldering. Optimal Au thickness is essential; Au thickness should be thick enough for reliable soldering, but must also be thin enough to offset the high cost and to prevent formation of a brittle Au-rich IMC layer in the solder joint. AuIn2 is the preferred IMC for indium-gold soldering and does not embrittle the solder joint. Resulting IMC type depends on the Au:In ratio which can be predicted by a In-Au binary phase diagram. On this basis, critical Au plating thickness to form AuIn2 IMC can be estimated using the known density values for electroplated gold and indium. In this study, Au thicknesses ranging from 0.035 to 0.2μm with a fixed gold pad size were electrolytically plated on a nickel plated copper lid. Assembled units were then subjected to Temperature Cycling-B (TCB). An in-house developed metrology for measuring junction-to-case thermal impedance (Rjc) is described. In this study, varying the thermal lids Au-plating thickness between 0.035 to 0.2 μm only lead to slight increase in center and corner Rjc values through 115 cycles TCB. The maximum center Rjc degradation post thermal cycling observed was only ∼ 1.7% on the lids with Au pad thickness between 0.035 – 0.04 μm. There were also no clear indications of impact of Au pad thickness on center and corner Rjc performance at EOL or post 115 cycles TCB. Thermal lids/TIM interface integrity remains unchanged for the range of Au pad thickness considered. However, detailed scanning electron microscopy and energy dispersive spectroscopy showed thicker Au plating results in greater incidence of AuIn2 IMC nodules beneath In-Ni-Au ternary IMC layer at end of line (EOL) ie post packaging and test. AuIn2 IMC is formed right after assembly and is what that holds the solder to the lid. As such, it follows that the presence of a more continuous and possibly greater number of AuIn2 IMC nodules can be expected to provide a better lid-solder joint at EOL.

SIF Prediction of Nanocomposite With Interfacial Debonding

2014 ◽  
Author(s):  
Waleed K. Ahmed
Keyword(s):  
Representative Volume Element ◽  
Volume Element ◽  
Uniaxial Tensile ◽  
Element Analysis ◽  
Linear Elastic ◽  
Composite Failure ◽  
Representative Volume ◽  
Uniaxial Tensile Stress ◽  
Composite Stiffness ◽  
The Impact

Local debonding in nanofiber/matrix interface of a nanofiber reinforced composite has been considered as one of the most important factors that can significantly reduce the composite stiffness as well as increases the interfacial stresses levels which eventually causes composite failure. In the present study, the debonded zone is considered as an interfacial defect and modeled to be a circumferential crack. Linear Elastic Fracture Mechanic (LEFM) was used to investigate the impact of a nanofiber/matrix debonded interface in a nanocomposite through estimating Stress Intensity Factor (SIF). Finite element analysis (FEA) has been carried out to investigate SIF along the debonded edge using 3D-axisymmetric method, and this was done through modeling half of the representative volume element (RVE). A representative volume element of the nanocomposite was modeled and analyzed to explore SIF. Mainly, RVE consists of a nanofiber confined by a matrix and subjected to uniaxial tensile stress. A longitudinal debonding is proposed along the interfacial nanofiber/matrix. It has been shown that FE results indicates a significant impact of the debonding on the SIF of the nanocomposite.

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