Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

Optimization of a Flux-Less Metal Thermal Interface Material by Reflow in a Vacuum Furnace

2011 ◽  
Vol 2011 (1) ◽  
pp. 000929-000937
Author(s):  
Pierino I Zappella ◽  
Paul W Barnes ◽  
David Muhs ◽  
Bruce Wilson
Keyword(s):  
Flip Chip ◽  
Pure Metal ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Vacuum Furnace ◽  
Acceptance Criteria ◽  
Specific Sequence ◽  
Thermal Interface ◽  
Series Of Experiments ◽  
Initial Objective

This paper describes the work performed with a pure metal thermal interface material (TIM) for the sole purpose to improve the transfer of heat from the die to the metal cover case. A flux-less reflow process is employed in order to reflow the indium TIM material. This operation is performed in a vacuum furnace utilizing heat, vacuum, and pressure in a specific sequence in order to wet the metal lid and the backside of the flip chip die. The initial objective was to demonstrate minimal voiding of the TIM and subsequently limited flow out of molten solder from and along the sides of the die. A series of experiments were employed where acceptance criteria is evaluated by a) X-Ray, b) scanning acoustical microscopy (SAM), and c) cross-section. Acceptance criteria consists of 1) indium wetting of both lid to indium interface and indium to silicon interface die, 2) indium bond line (BLT) thickness, 3) lid tilt, and 4) lid shear strength. Acceptance is determined after a subsequent 4X ball grid array (BGA) reflow in a conventional belt reflow furnace with minimal voiding, no popcorn or blistering of the laminate substrate, and TIM thickness and solder flow out at sides of the die within the acceptable limits of the above mentioned criteria.

Prospects for automotive SiP modules applying IC assembly and packaging technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000006-000012
Author(s):  
Tomohiro Furukawa ◽  
Takahiro Kasuga ◽  
Masato Umehara ◽  
Yuka Tamadate
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Interface Material ◽  
Heat Sources ◽  
Heat Spreader ◽  
Thermal Interface ◽  
Passive Components ◽  
Reflow Temperature ◽  
Assembly Technology

Abstract We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules. It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.

Using In situ Capacitance Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies

2010 ◽  
Vol 2010 (1) ◽  
pp. 000450-000457
Author(s):  
Michael Gaynes ◽  
Timothy Chainer ◽  
Edward Yarmchuk ◽  
John Torok ◽  
David Edwards ◽  
...  
Keyword(s):  
Thermal Cycle ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Circuit Board ◽  
Large Area ◽  
Voltage Transformer ◽  
Heat Spreader ◽  
Thermal Interface ◽  
Thermal Solution

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface. This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process. The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area. Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.

Precise, high throughput dispensing of thermal interface material in BGA packaging applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001391-001412
Author(s):  
Hanzhuang Liang ◽  
Linh Rolland
Keyword(s):  
High Throughput ◽  
Flip Chip ◽  
Consumer Electronics ◽  
Thermal Interface Material ◽  
Production Lines ◽  
Heat Spreader ◽  
Heavy Load ◽  
Thermal Interface ◽  
Wide Range ◽  
Complicated Geometries

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

Finite element analysis of lidded flip-chip packages: A study on the impact of thermal interface material compressibility and stress-free conditions on modeling predictions

2015 ◽  
Vol 2015 (1) ◽  
pp. 000151-000156
Author(s):  
Tuhin Sinha
Keyword(s):  
Flip Chip ◽  
Image Correlation ◽  
Thermal Interface Material ◽  
Element Analysis ◽  
Thermal Interface ◽  
Strong Function ◽  
Linear Elastic ◽  
Fea Modeling ◽  
Predicted Values ◽  
The Impact

In this paper, we present the effects of assumptions made about the constitutive behavior of a cured, silicone gel type thermal interface material (TIM) and the package stress-free conditions on FEA modeling predictions. The focus will be on the deformations (or warpage) predicted by the models for lidded flip-chip packages. It is critical for such warpage predictions to be close to experimental measurements for accurate projection of mechanical stresses and strains in a package. Digital Image Correlation (DIC) warpage measurements on flip-chip modules are compared against the predicted values and the impact of above-mentioned assumptions will be discussed. It will be shown that the TIM mechanical and thereby, thermal degradation is a strong function of the TIM compressibility and stress-free condition assumptions. Bounds of non-linear elastic modeling technique for the TIM and guidelines for conducting numerical analysis for lidded flip-chip packages will be provided.

Joint Healing Thermal Interface Material

2016 ◽  
Vol 2016 (1) ◽  
pp. 000482-000489 ◽  
Author(s):  
Jingting Yang ◽  
Jason Strader ◽  
Sean Orzolek ◽  
Eugene Pruss ◽  
Phillip Fosnot ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Coefficient Of Thermal Expansion ◽  
Current Trend ◽  
Thermal Interface Material ◽  
Circuit Board ◽  
Conduction Path ◽  
Thermal Interface ◽  
Application Study ◽  
Cte Mismatch ◽  
Additional Value

Abstract Today, thermal interface materials (TIM) are widely used between a processor die and an integrated heat-spreader (IHS) to provide a good thermal conduction path for heat transfer from the electronic package. As the current trend towards larger “die size designs” progresses, the performance and reliability of the TIM will be a greater challenge for thermal engineers. In these larger die size designs, the TIM will experience increased movement as a result of the coefficient of thermal expansion (CTE) mismatch between the die and the printed circuit board. Traditionally, indium and dispensable thermoset materials are utilized in this application. However, delamination of the TIM from one of the mating surfaces is becoming more common as these materials are unable to compensate for the increased movement. In addition, the increasing cost of indium metal is causing indium-based TIMs to become cost prohibitive while dispensable materials require frozen shipment and storage, creating logistics complications and increased costs. A recently concluded application study demonstrated that a joint-healing thermoplastic pad had better performance after thermal shock cycling, when compared to typically used TIMs. The joint-healing, thermoplastic pad maintained lower thermal resistance at the center and edges of the die. The soft thermoplastic nature of this material helps prevent delamination, or pump out, during cycling and is capable of joint-healing most delaminations that occur at operating temperatures. Data at various intervals ending at 1000 cycles will be presented. The ability to ship and store this material at room temperature as well as pre-apply it to the IHS adds additional value by simplifying logistics and reducing cost.

Effects of Thermal Lids Gold Plating Thickness on Thermal Interface Reliability for Flip Chip Packaging

2007 ◽  
Author(s):  
Chin Hock Toh ◽  
Arun Raman ◽  
Thomas Fitzgerald ◽  
Madhuri Narkhede ◽  
Alfred A. La Mar ◽  
...  
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Thermal Interface Material ◽  
Thermal Impedance ◽  
Thermal Reliability ◽  
Gold Plating ◽  
Thermal Interface ◽  
Density Values ◽  
Flip Chip Packaging

This paper summarizes the intermetallic compounds (IMC) formation at the interface between thermal interface material (TIM) and nickel/gold plated integrated heat spreader (IHS) at varying Au thickness, and its impact on thermal reliability. Indium solders due to their high thermal conductivity are commonly used as the TIM to dissipate heat from silicon die to the thermal lids for new generation microprocessors with higher operating die temperatures. Indium solders readily wet the Au plating on thermal lids to form IMC during soldering. Optimal Au thickness is essential; Au thickness should be thick enough for reliable soldering, but must also be thin enough to offset the high cost and to prevent formation of a brittle Au-rich IMC layer in the solder joint. AuIn2 is the preferred IMC for indium-gold soldering and does not embrittle the solder joint. Resulting IMC type depends on the Au:In ratio which can be predicted by a In-Au binary phase diagram. On this basis, critical Au plating thickness to form AuIn2 IMC can be estimated using the known density values for electroplated gold and indium. In this study, Au thicknesses ranging from 0.035 to 0.2μm with a fixed gold pad size were electrolytically plated on a nickel plated copper lid. Assembled units were then subjected to Temperature Cycling-B (TCB). An in-house developed metrology for measuring junction-to-case thermal impedance (Rjc) is described. In this study, varying the thermal lids Au-plating thickness between 0.035 to 0.2 μm only lead to slight increase in center and corner Rjc values through 115 cycles TCB. The maximum center Rjc degradation post thermal cycling observed was only ∼ 1.7% on the lids with Au pad thickness between 0.035 – 0.04 μm. There were also no clear indications of impact of Au pad thickness on center and corner Rjc performance at EOL or post 115 cycles TCB. Thermal lids/TIM interface integrity remains unchanged for the range of Au pad thickness considered. However, detailed scanning electron microscopy and energy dispersive spectroscopy showed thicker Au plating results in greater incidence of AuIn2 IMC nodules beneath In-Ni-Au ternary IMC layer at end of line (EOL) ie post packaging and test. AuIn2 IMC is formed right after assembly and is what that holds the solder to the lid. As such, it follows that the presence of a more continuous and possibly greater number of AuIn2 IMC nodules can be expected to provide a better lid-solder joint at EOL.

Reliability Analysis of Flip Chip Designs Via Computer Simulation

2000 ◽  
Vol 122 (3) ◽  
pp. 214-219 ◽  
Author(s):  
Hua Lu ◽  
C. Bailey ◽  
M. Cross
Keyword(s):  
Material Properties ◽  
Flip Chip ◽  
Thermal Loading ◽  
Coefficient Of Thermal Expansion ◽  
Empirical Relationship ◽  
Life Time ◽  
Fatigue Reliability ◽  
Chip Design ◽  
Flip Chips ◽  
Out Of Plane

A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young’s modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE CTEz of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias. [S1043-7398(00)01203-2]

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