Enhanced Mpilog macromodels for Signal and Power Integrity Simulations

2015 ◽  
Vol 2015 (1) ◽  
pp. 000306-000311
Author(s):  
Gianni Signorini ◽  
Claudio Siviero ◽  
Igor Simone Stievano ◽  
Stefano Grivet-Talocia
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
State Of The Art ◽  
Low Cost ◽  
System Level ◽  
Power Integrity ◽  
Mobile Platforms ◽  
Power Supply Voltage ◽  
Dynamic Components ◽  
Small Form Factor

Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.). In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations. This work summarizes the recent enhancements of “Mpilog”-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The static parts are extracted via nested DC sweeps simulations and reproduced by tensor representations obtained via high-order singular value decomposition (SVD) processes. The dynamic components are described by linear state-space models identified from device's transient responses to suitable stimuli. For transmitters, the weighting functions match the output-port transitions and the dynamic supply-current profiles, capturing also the dependency of switching delays upon supply-voltage fluctuations; this is a key feature that enables Mpilog macromodels to precisely reproduce simultaneous-switching-noise (SSN) effects in complex system-level SI&PI simulations. The macromodels can be readily synthesized as SPICE netlists (including resistors, capacitors and controlled-sources) or Verilog-A codes; this allows their use in any SPICE-type electrical solver. Several examples of realistic SI&PI simulations for single-ended and differential interfaces are presented. Transistor-level simulations are compared with the corresponding ones based on Mpilog-macromodels: the resulting accuracy and the speed-up factors are extensively discussed. Comparisons with state-of-the-art legacy models (IBIS) are also discussed.

High‐speed low‐power and low‐power supply voltage dynamic comparator

2015 ◽  
Vol 51 (23) ◽  
pp. 1914-1916 ◽  
Author(s):  
Daiguo Xu ◽  
Shiliu Xu ◽  
Guangbing Chen
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Dynamic Comparator

Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15
Author(s):  
Hong Xie ◽  
Daquan Yu ◽  
Zhenrui Huang ◽  
Zhiyi Xiao ◽  
Li Yang ◽  
...  
Keyword(s):  
Form Factor ◽  
High Speed ◽  
Low Cost ◽  
High Density ◽  
Wafer Level ◽  
Small Form ◽  
Wafer Level Packaging ◽  
Temporary Bonding ◽  
Small Form Factor ◽  
Si Wafer

The growing and diversifying system requirements have continued to drive the development of a variety of new package technologies and configurations: small form factor, low weight, low profile, high pin count and high speed and low cost. Embedded chip in EMC, also called fan-out wafer-level packaging (FOWLP), has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs). Currently, INFO technology developed by TSMC®, NANIUM® were in mass production for 3D integration for processor and memory, which inspires other packaging foundries to develop their own embedded FOWLP for the forecasted explosive growth of this market in the next few years. There are a number of challenges for FOWLP. For process point of view, temporary bonding and de-bonding are required. EMC wafers are difficult to handle due to its large warpage driven by the big CTE difference between the Si and molding material. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. In this paper, the concept of wafer level embedded Si Fan-Out (eSiFO) technology was introduced and the development progress was reported. For eSiFO, cavities with certain depth were formed by Si dry etch. Then device dies were thinned to designed thickness. The dice were then placed into the cavities and bonded by the attached film on the bottom of the dice. A reconstructed wafer was formed. The micro gap between the chip and sidewall of the cavity as well as the surface of the reconstructed wafer were filled by dry film using vacuum process. Next, the pads were opened, followed RDL fabrication, repassivation, BGA, wafer thinning and dicing. Finally, an eSiFO package was fabricated. There are a number of advantages for eSiFO technology. There is nearly no warpage since the Si was used as reconstruct substrate. The process is relatively simple since no molding, temporary bonding and de-bonding are required. RDL manufacturing is easier on Si wafer vs with molding compounds and can achieve high density routing. Furthermore, it can provide small form factor since the thinning of wafer is the last step. To prove the concept of eSiFO, a 3.3 x 3.3mm package with 50 BGA bumps at 400μm pitch was fabricated. The device wafer was thinned to 100μm. The die size is 1.96 × 2.36mm with pad pitch at about 90μm. The depth of the cavities on 8 in. wafer formed by Bosch process on bare Si wafer was 107μm with 8μm variation. The length and width of Si cavities is 20μm larger than die size. In the package, there is one layer Cu RDL with thickness of 3μm, minimum line width of 13.72μm. The BGA ball diameter is 280μm. All the processes were evaluated and the results showed such packages can be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure issue was observed. Mechanical simulation was used to analyze the stress distribution during TC test and the results showed the maximum stress was located at the RDL near the UBM. In summary, a low cost wafer level fan out technology using reconstructed Si wafer was developed. The process is simple without molding, temporary bonding and de-bonding. The reliability tests of test vehicles proved that such package is reliable. The newly developed eSiFO technology can be widely used for chips requiring fan-Out, small form factor and high density interconnects.

Method for system-level signal and power integrity modeling of high-speed electronic packages

2009 ◽  
Author(s):  
En-Xiao Liu ◽  
Xingchang Wei ◽  
Zaw Zaw OO ◽  
Yao-Jiang Zhang ◽  
Wenzu Zhang ◽  
...  
Keyword(s):  
High Speed ◽  
System Level ◽  
Electronic Packages ◽  
Power Integrity

Integral Type Multi-Ramp for Single-Slope ADC

2013 ◽  
Vol 303-306 ◽  
pp. 1908-1912 ◽  
Author(s):  
Nan Lyu ◽  
Ning Mei Yu ◽  
He Jiu Zhang
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Supply Voltage ◽  
High Accuracy ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Voltage Reference ◽  
Integral Type ◽  
Power Supply Voltage ◽  
The One

This paper presents a integral type Multi-ramp architecture apply to MRSS ADC (Multiple-ramp single-slope ADC).On the one hand to improve the capacitance mismatch by change voltage reference, On the other hand to reduced the power consumption greatly. Implemented in the GSMC 180nm 2P4M CMOS process, in the power supply voltage of 1.8 V, 11-bit resolution, 10 MHZ sampling frequency, the result of max power consumption is 1.33mW of single unit .The DNL < 0.1LSB and max INL < 0.49LSB .The Multi-ramp achieved requirements for high speed and high accuracy MRSS ADC.

A High-Speed and High-Linearity BiCMOS Optically Coupled Isolation Amplifier

2012 ◽  
Vol 241-244 ◽  
pp. 2200-2203
Author(s):  
Shu Han Li ◽  
Ning Yang ◽  
Li Cheng ◽  
Sheng Hua Zhang
Keyword(s):  
Power Supply ◽  
High Speed ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Power Product ◽  
High Linearity ◽  
Isolation Amplifier ◽  
Amplifier Gain ◽  
High Power Consumption ◽  
Output Stages

To improve the current non-linear optically coupled isolation amplifier and high power consumption, we designed a low-power, high-speed and high-linearity BiCMOS optically isolation amplifier. There are only two push-pull output stages configuration bipolar transistor (BJT) in the design process, the rest of the circuit is the CMOS device. To improve amplifier gain linearity and stability, we introduce the complementary symmetrical photodiode, in the optically coupled part and every amplifier, negative feedback is introduced. Experimental results indicate that the design of optically isolation amplifier ± 3 dB bandwidth increases 40 kHz than optically isolation amplifier ISO100 bipolar, When the power supply voltage is 4.8 V, the delay - power product of DP is lower than ISO100 37.3 pJ, gain linearity is up to 5.5 × 10-5, which is suitable for high-speed control system.

scholarly journals VLC Network Design for High Mobility Users in Urban Tunnels

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 88
Author(s):  
Edmundo Torres-Zapata ◽  
Victor Guerra ◽  
Jose Rabadan ◽  
Martin Luna-Rivera ◽  
Rafael Perez-Jimenez
Keyword(s):  
Network Design ◽  
Intelligent Transportation Systems ◽  
High Speed ◽  
Vehicular Networks ◽  
Low Cost ◽  
High Mobility ◽  
Visible Light Communication ◽  
Transportation Systems ◽  
System Level ◽  
On The Road

Current vehicular systems require real-time information to keep drivers safer and more secure on the road. In addition to the radio frequency (RF) based communication technologies, Visible Light Communication (VLC) has emerged as a complementary way to enable wireless access in intelligent transportation systems (ITS) with a simple design and low-cost deployment. However, integrating VLC in vehicular networks poses some fundamental challenges. In particular, the limited coverage range of the VLC access points and the high speed of vehicles create time-limited links that the existing handover procedures of VLC networks can not be accomplished timely. Therefore, this paper addresses the problem of designing a vehicular VLC network that supports high mobility users. We first modify the traditional VLC network topology to increase uplink reliability. Then, a low-latency handover scheme is proposed to enable mobility in a VLC network. Furthermore, we validate the functionality of the proposed VLC network design method by using system-level simulations of a vehicular tunnel scenario. The analysis and the results show that the proposed method provides a steady connection, where the vehicular node is available more than 99% of the time regardless of the number of vehicular nodes on this network. Additionally, the system is able to achieve a Frame-Error-Rate (FER) performance lower than 10−3.

Autonomous Flight

2018 ◽  
Vol 1 (1) ◽  
pp. 29-52 ◽  
Author(s):  
Sarah Tang ◽  
Vijay Kumar
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Low Cost ◽  
Research Trends ◽  
Multirobot Systems ◽  
Future Research ◽  
Full Vehicle ◽  
Current State ◽  
Tremendous Progress ◽  
New Research

This review surveys the current state of the art in the development of unmanned aerial vehicles, focusing on algorithms for quadrotors. Tremendous progress has been made across both industry and academia, and full vehicle autonomy is now well within reach. We begin by presenting recent successes in control, estimation, and trajectory planning that have enabled agile, high-speed flight using low-cost onboard sensors. We then examine new research trends in learning and multirobot systems and conclude with a discussion of open challenges and directions for future research.

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