Designing a Full Adder Circuit Based on Quasi-Floating Gate

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

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Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1998p0289 ◽

1998 ◽

Author(s):

H. Lorenz ◽

C. Engel

Keyword(s):

Focused Ion Beam ◽

Cell Function ◽

Dielectric Breakdown ◽

Ion Beam ◽

Electrical Characterization ◽

Floating Gate ◽

Leakage Path ◽

Contrast Technique ◽

Voltage Contrast

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

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Full adder design based on hybrid logic of M4 structure

JOURNAL OF SHENZHEN UNIVERSITY SCIENCE AND ENGINEERING ◽

10.3724/sp.j.1249.2014.05479 ◽

2014 ◽

Vol 31 (5) ◽

pp. 479

Author(s):

Yinshui Xia ◽

Shiheng Wang ◽

Libo Qian

Keyword(s):

Full Adder ◽

Hybrid Logic

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Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513666200107091932 ◽

2020 ◽

Vol 13 (6) ◽

pp. 864-870

Author(s):

Sai Venkatramana Prasada G.S ◽

G. Seshikala ◽

S. Niranjana

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

High Performance ◽

Full Adder ◽

Fundamental Operation ◽

Wallace Tree ◽

Power Delay Product ◽

The Comparative Study ◽

Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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