scholarly journals A novel approach for road surface wetness detection with planar capacitive sensors

2019 ◽  
Vol 8 (1) ◽  
pp. 57-66 ◽  
Author(s):  
Jakob Döring ◽  
Lakshan Tharmakularajah ◽  
Jakob Happel ◽  
Karl-Ludwig Krieger
Keyword(s):  
Printed Circuit Board ◽  
Test Bench ◽  
Motor Vehicle ◽  
Road Surface ◽  
Circuit Board ◽  
Design Parameters ◽  
Capacitive Sensors ◽  
Surface Wetness ◽  
Novel Approach ◽  
Wheel Arch

Abstract. This paper presents a novel approach for detecting road surface wetness with planar capacitive sensors on the wheel arch liner of a motor vehicle. For this purpose, various design parameters of interdigital electrodes are studied by means of the finite element method (FEM). A suitable design for the detection of whirled-up water is proposed, which is manufactured on a flexible printed circuit board (PCB) and investigated in an experimental study. A test bench is built for that purpose, which includes a motor vehicle's front wheel arch liner and can simulate realistic road surface wetness conditions. Experimental results show the possibility of distinguishing between different road wetness conditions and confirm that a static wetting of the wheel arch liner can be detected. Finally, an application-specific sensor system is proposed, which is validated by experiments on a test bench and is integrated into a vehicle. Field test results show the feasibility of detecting different road wetness levels and demonstrate the potential of the presented approach.

scholarly journals Wideband Rectangular Foldable and Non-foldable Antenna for Internet of Things Applications

2019 ◽  
Vol 2019 ◽  
pp. 1-5 ◽  
Author(s):  
Steve W. Y. Mung ◽  
Cheuk Yin Cheung ◽  
Ka Ming Wu ◽  
Joseph S. M. Yuen
Keyword(s):  
Internet Of Things ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Design Parameters ◽  
Multiple Frequency ◽  
Wireless Applications ◽  
Printed Circuit ◽  
Iot Applications ◽  
Trade Offs ◽  
The Cost

This article presents a simple wideband rectangular antenna in foldable and non-foldable (printed circuit board (PCB)) structures for Internet of Things (IoT) applications. Both are simple structures with two similar rectangular metal planes which cover multiple frequency bands such as GPS, WCDMA/LTE, and 2.4 GHz industrial, scientific, and medical (ISM) bands. This wideband antenna is suitable to integrate into the short- and long-range wireless applications such as the short-range 2.4 GHz ISM band and standard cellular bands. This lowers the overall size of the product as well as the cost in the applications. In this article, the configuration and operation principle are presented as well as its trade-offs on the design parameters. Simulated and experimental results of foldable and non-foldable (PCB) structures show that the antenna is suited for IoT applications.

Dynamic Modeling of Tape Head Actuator Lateral Motion With Elastica Suspension

2011 ◽  
Author(s):  
Jen-Yuan James Chang
Keyword(s):  
Printed Circuit Board ◽  
High Capacity ◽  
Voice Coil Motor ◽  
Dynamic Effect ◽  
Magnetic Suspension ◽  
Circuit Board ◽  
Design Parameters ◽  
Lateral Motion ◽  
Printed Circuit ◽  
Flexible Printed Circuit

A combined elastica and magnetic modeling is presented in this paper with focus given to understanding effect of flexible printed circuit cable and voice coil motor’s dynamic effect on tape head actuator’s lateral motion in advanced, high capacity tape drives. The flexible printed circuit cable which connects the actuator to printed circuit board is first examined through establishment of analytical model to predict its profile with considerations of boundary conditions and mechanical design parameters. Secondly, equivalent stiffness produced by the flexible printed circuit cable when the linear tape head actuator is positioned along its lateral positions is examined. Finally, effect of tape head actuator’s voice coil motor is studied and modeled as a magnetic suspension, contributing to stability and controllability of the actuator lateral motion dynamics. Validated by calibrated laboratory experiments, the work presented in this paper can add to the literature regarding dynamics and control of LTM in modern LTO drives.

Damage and Failures of CGA/BGA Assemblies Under Thermal Cycling and Dynamic Loadings

2013 ◽  
Author(s):  
Reza Ghaffarian
Keyword(s):  
Thermal Cycling ◽  
Mechanical Loading ◽  
Test Data ◽  
Printed Circuit Board ◽  
High Reliability ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Space Applications ◽  
High Processing

Commercial-off-the-shelf column/ball grid array packaging (COTS CGA/BGA) technologies in high-reliability versions are now being considered for use in high-reliability electronic systems. For space applications, these packages are prone to early failure due to the severe thermal cycling in ground testing and during flight, mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of solder interconnections decreases, susceptibility to thermal, mechanical loading and cycling fatigue grows even more. This paper reviews technology as well as thermo-mechanical reliability of field programmable gate array (FPGA) IC packaging developed to meet demands of high processing powers. The FPGAs that generally come in CGA/PBGA packages now have more than thousands of solder balls/columns under the package area. These packages need not only to be correctly joined onto printed circuit board (PCB) for interfacing; they also should show adequate system reliability for meeting thermo-mechanical requirements of the electronics hardware application. Such reliability test data are rare or none for harsher environmental applications, especially for CGAs having more than a thousand of columns. The paper also presents significant test data gathered under thermal cycling and drop testing for high I/O PBGA/CGA packages assembled onto PCBs. Damage and failures of these assemblies after environmental exposures are presented in detail. Understanding the key design parameters and failure mechanisms under thermal and mechanical conditions is critical to developing an approach that will minimize future failures and will enable low-risk insertion of these advanced electronic packages with high processing power and in-field re-programming capability.

scholarly journals Analytical modeling of multi-layered printed circuit board using multi-stacked via clusters as component heat spreader

2016 ◽  
Vol 20 (5) ◽  
pp. 1633-1647 ◽  
Author(s):  
Eric Monier-Vinard ◽  
Najib Laraqi ◽  
Cheikh Dia ◽  
Minh-Nhat Nguyen ◽  
Valentin Bissuel
Keyword(s):  
Analytical Model ◽  
Printed Circuit Board ◽  
Electronics Cooling ◽  
Circuit Board ◽  
Design Parameters ◽  
Board Structure ◽  
Printed Circuit ◽  
Fourier Series Method ◽  
Potential Gain ◽  
Local Modification

In order to help the electronic designer to early determine the limits of the power dissipation of electronic component, an analytical model was established to allow a fast insight of relevant design parameters of a multi-layered electronic board constitution. The proposed steady-state approach based on Fourier series method promotes a practical solution to quickly investigate the potential gain of multi-layered thermal via clusters. Generally, it has been shown a good agreement between the results obtained by the proposed analytical model and those given by electronics cooling software widely used in industry. Some results highlight the fact that the conventional practices for Printed Circuit Board modeling can be dramatically underestimate source temperatures, in particular with smaller sources. Moreover, the analytic solution could be applied to optimize the heat spreading in the board structure with a local modification of the effective thermal conductivity layers.

Embedded Passives: A Novel Approach Using Ceramic Thick Film Technology

2003 ◽  
Author(s):  
Richard C. Snogren
Keyword(s):  
Thick Film ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Passive Components ◽  
Average Cell ◽  
Novel Approach ◽  
Wide Range ◽  
Embedded Passives ◽  
Improved Performance ◽  
Range Of Values

This paper is an in depth presentation of a novel approach for design and manufacturing processes to embed ceramic thick film resistors and discrete capacitors into circuit board substrates. These robust materials are available in a wide range of values. Embedded passives, i.e., resistors and capacitors built right into the printed circuit board substrate will be the next pivotal technology for the PCB industry, preceded by the plated thru hole in the 50s, and microvias in the 90s. Key drivers are performance, miniaturization, and cost. The average cell phone has 445 SMT passive components at a 25:1 ratio to ICs. Embedding many of these will improve performance, enable more functionality and reduce cost per function. Embedded passives are not limited to cell phones, many other applications will benefit from improved performance. Several materials are commercially available today and many new materials are in development.

Localization of component lead inside a THT solder joint for solder defects classification

2017 ◽  
Vol 2 (83) ◽  
pp. 57-66 ◽  
Author(s):  
C.L.S.C. Fonseka ◽  
J.A.K.S. Jayasinghe
Keyword(s):  
Quality Assurance ◽  
Solder Joint ◽  
Template Matching ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Precise Localization ◽  
Soldering Process ◽  
Novel Approach ◽  
Defects Classification

Purpose: Automatic Optical Inspection (AOI) systems, used in electronics industry have been primarily developed to inspect soldering defects of Surface Mount Devices (SMD) on a Printed Circuit Board (PCB). However, no commercially available AOI system exists that can be integrated to a desktop soldering robotic system, which is capable of identifying soldering defects of Through Hole Technology (THT) solder joints along with the soldering process. In our research, we have implemented an AOI platform that is capable of performing automatic quality assurance of THT solder joints in a much efficient way. In this paper, we have presented a novel approach to identify soldering defects of THT solder joints, based on the location of THT component lead top. This paper presents the methodologies that can be used to precisely identify and localize THT component lead inside a solder joint. Design/methodology/approach: We have discussed the importance of lead top localization and presented a detailed description on the methodologies that can be used to precisely segment and localize THT lead top inside the solder joint. Findings: It could be observed that the precise localization of THT lead top makes the soldering quality assurance process more accurate. A combination of template matching algorithms and colour model transformation provide the most accurate outcome in localizing the component lead top inside solder joint, according to the analysis carried out in this paper. Research limitations/implications: When the component lead top is fully covered by the soldering, the implemented methodologies will not be able to identify the actual location of it. In such a case, if the segmented and detected lead top locations are different, a decision is made based on the direction in which the solder iron tip touches the solder pad. Practical implications: The methodologies presented in this paper can be effectively used to have a precise localization of component lead top inside the solder joint. The precise identification of component lead top leads to have a very precise quality assurance capability to the implemented AOI system. Originality/value: This research proposes a novel approach to identify soldering defects of THT solder joints in a much efficient way based on the component lead top. The value of this paper is quite high, since we have taken all the possibilities that may appear on a solder joint in a practical environment.

Investigating and compensating printed circuit board shrinkage induced failures during reflow soldering

2015 ◽  
Vol 27 (2) ◽  
pp. 61-68 ◽  
Author(s):  
Attila Geczy ◽  
Márta Fejos ◽  
László Tersztyánszky
Keyword(s):  
Efficient Method ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Automotive Electronics ◽  
Production Environment ◽  
Reflow Soldering ◽  
Content Type ◽  
Printed Circuit ◽  
Novel Approach ◽  
The Given

Purpose – This paper aims to reveal the causes and find an efficient method to compensate the shrinkage to reduce failure costs. Reflow-induced printed circuit board (PCB) shrinkage is inspected in automotive electronics production environment. The shrinkage of two-sided, large PCBs results in printing offset errors and consequently soldering failures on smaller components during the reflow soldering of the second PCB side. Design/methodology/approach – During the research, the investigations had to adapt to actual production in an electronics manufacturing plant. A measurement method was developed to approximate the overall shrinkage of the given product. With the shrinkage data, it is possible to perform an efficient compensation on the given stencil design in computer-aided manufacturing environment. Findings – It was found that even with the investigated lower-quality PCB materials, the compensation on the stencil significantly reduces the quantity of failures, offering an efficient method to improve the yield of the production. Research limitations/implications – Research was oriented by the confines of production (fixed PCB sources, given PCB materials, reflow process and production line), where an immediate solution is needed. Future investigations should be focussed on the PCB parameters (different epoxy types, glass-fibre reinforcements, etc.). Practical implications – The optimised production reduces overall failure costs. The stencil re-design and application is a fast and efficient way to immediately act against the shrinkage-induced failures. The method was successfully applied in automotive electronics production. Originality/value – The paper presents a novel approach on solving an emerging problem during reflow.

A Novel Approach to Identifying and Validating Electrical Leakage in Printed Circuit Boards Through Magnetic Current Imaging

2004 ◽  
Author(s):  
Craig Hillman
Keyword(s):  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Ground Plane ◽  
Circuit Board ◽  
Magnetic Current ◽  
Printed Circuit ◽  
Root Cause ◽  
Low Leakage ◽  
Novel Approach ◽  
Failure Site

Abstract Superconducting Quantium Interferance Device (SQUID) microscopy uses detection of magnetic fields to image current paths within electronic devices and has been successful in non-destructively identifying the location of low leakage currents, even when the failure site was between a power and ground plane. This article presents a case study in which the customer was experiencing ignition of a 20-layer printed circuit board after approximately 1000 to 4000 operating hours in an indoor-controlled environment. High currents on the board resulted in extensive damage, effectively preventing initial identification of the failure site, failure mechanism, or root-cause. Based on a review of potential failure mechanisms, measurement of relevant parameters, and the results of SQUID microscopy, the process of electrochemical migration around or through the particles was determined to be the most likely root-cause of electrical shorting between power and ground.

Heat Conduction in Printed Circuit Boards: A Mesoscale Modeling Approach

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Design Parameters ◽  
Internal Layers ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Covered Area ◽  
Bga Package ◽  
Cooling Air

An analytical model is developed to estimate the heat transfer performance of printed circuit board (PCBs). The PCB under study is the substrate for a ball-grid-array (BGA) package. Under the BGA, the PCB has a belt of densely populated through-vias that penetrate the laminate of horizontal copper and resin; outside the BGA-covered area the board is a copper/resin laminate and its surfaces are exposed to cooling air. Calculations are performed on a sample board having the dimensions 11×11 cm2 (footprint)×1.26 mm (thickness). The model of the board has two internal layers of continuous copper (0.03 mm thick) and through-vias under a 4.4×4.4 cm2 BGA package. The impacts of board design parameters on the temperature and the heat flow are presented; the parameters are the width of the insulation gap around the via, the area of copper coverage at the via bottom, and the population of vias.

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