scholarly journals Design Optimization of Silicon-based Junctionless Fin-type Field-Effect Transistors for Low Standby Power Technology

2013 ◽  
Vol 8 (6) ◽  
pp. 1497-1502 ◽  
Author(s):  
Jae Hwa Seo ◽  
Heng Yuan ◽  
In Man Kang
Keyword(s):  
Design Optimization ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Standby Power ◽  
Silicon Based

scholarly journals DESIGN OPTIMIZATION OF EXTREMELY SHORT-CHANNEL GRADED SI/SIGE HETEROJUNCTION TUNNEL FIELD-EFFECT TRANSISTORS FOR LOW POWER APPLICATIONS

2018 ◽  
Vol 51 (6) ◽  
pp. 757
Author(s):  
Nguyen Dang Chien
Keyword(s):  
Design Optimization ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Subthreshold Swing ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Low Threshold ◽  
Standby Power ◽  
Dimensional Simulation

This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on- and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 1020 cm-3,                1018 cm-3, and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 μA/μm, low off-current of 0.5 pA/μm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques.

Effect of Ge Mole Fraction on Performance of Underlapped Gate-All-Around SiGe-Source Tunneling Field-Effect Transistors

2021 ◽  
Vol 21 (8) ◽  
pp. 4310-4314
Author(s):  
Juhee Jeon ◽  
Young-Soo Park ◽  
Sola Woo ◽  
Doohyeok Lim ◽  
Jaemin Son ◽  
...  
Keyword(s):  
Design Optimization ◽  
Mole Fraction ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Tunneling Barrier ◽  
Current Ratio ◽  
Threshold Voltages ◽  
Band To Band Tunneling ◽  
Tunneling Field Effect Transistors ◽  
Commercial Device

In this paper, we propose the design optimization of underlapped Si1–xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I–V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1–xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

Organic Materials for Multifunctional Transistor-Based Devices

2002 ◽  
Vol 725 ◽  
Author(s):  
H.E. Katz ◽  
T. Someya ◽  
B. Crone ◽  
X.M. Hong ◽  
M. Mushrush ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Organic Field Effect Transistors ◽  
Large Area ◽  
Microprocessor Technology ◽  
Silicon Based ◽  
Electronic Ink ◽  
Made In ◽  
Charge Channel

Organic field-effect transistors (OFETs) are “soft material” versions of accumulationmode silicon-based FETs, where a gate field across a dielectric induces a conductive charge channel at the interface of the dielectric with a semiconductor, between source and drain electrodes. Charge carrier mobilities >0.01 and on/off ratios >10,000 are routinely obtained, adequate for a few specialized applications such as electrophoretic pixel switches but well below standards established for silicon microprocessor technology. Still, progress that has been made in solution-phase semiconductor deposition and the printing of contacts and dielectrics stimulates the development of OFET circuits for situations where extreme low cost, large area, and mechanical flexibility are important. Circuits with hundreds of OFETs have been demonstrated and a prototype OFETcontrolled black-on-white “electronic ink” sign has been fabricated.

Design Optimization and Analysis of InGaAs-Based Junctionless Fin Type Field-Effect Transistors (FinFETs) with LG = 10 nm

2016 ◽  
Vol 16 (10) ◽  
pp. 10187-10192
Author(s):  
Min Su Cho ◽  
Jae Hwa Seo ◽  
Young Jun Yoon ◽  
Jung-Hee Lee ◽  
In Man Kang
Keyword(s):  
Design Optimization ◽  
Field Effect ◽  
Field Effect Transistors

scholarly journals Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Monica Bollani ◽  
Marco Salvalaglio ◽  
Abdennacer Benali ◽  
Mohammed Bouabdellaoui ◽  
Meher Naffouti ◽  
...  
Keyword(s):  
Field Effect ◽  
Large Scale ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Spontaneous Formation ◽  
Surface Energy Anisotropy ◽  
Energy Anisotropy ◽  
On Chip ◽  
Silicon Based ◽  
Nano Wires

AbstractLarge-scale, defect-free, micro- and nano-circuits with controlled inter-connections represent the nexus between electronic and photonic components. However, their fabrication over large scales often requires demanding procedures that are hardly scalable. Here we synthesize arrays of parallel ultra-long (up to 0.75 mm), monocrystalline, silicon-based nano-wires and complex, connected circuits exploiting low-resolution etching and annealing of thin silicon films on insulator. Phase field simulations reveal that crystal faceting and stabilization of the wires against breaking is due to surface energy anisotropy. Wires splitting, inter-connections and direction are independently managed by engineering the dewetting fronts and exploiting the spontaneous formation of kinks. Finally, we fabricate field-effect transistors with state-of-the-art trans-conductance and electron mobility. Beyond the first experimental evidence of controlled dewetting of patches featuring a record aspect ratio of $$\sim$$~1/60000 and self-assembled $$\sim$$~mm long nano-wires, our method constitutes a distinct and promising approach for the deterministic implementation of atomically-smooth, mono-crystalline electronic and photonic circuits.

Mixed-Dimensional WS2/GaSb Heterojunction for High-performance p-n Diode and Junction Field-Effect Transistor

2022 ◽  
Author(s):  
Zichao Cheng ◽  
Xiufeng Song ◽  
Lianfu Jiang ◽  
Lude Wang ◽  
Jiamin Sun ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Effect Transistor ◽  
P Type ◽  
Silicon Based

GaSb nanowires integrated on a silicon-based substrate are of great significance for p-type field-effect transistors. In particular, due to the continued miniaturization of circuits, such as avoiding complex dielectric engineering,...

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