scholarly journals Seedling vigour enhancement through nursery bed protection and mulching for yield enhancement in rabi rice

2021 ◽  
Vol 22 (4) ◽  
pp. 518-523
Author(s):  
S. MOHAPATRA ◽  
S.K. TRIPATHY ◽  
S. TRIPATHY
Keyword(s):  
Yield Enhancement ◽  
Seedling Vigour ◽  
Bed Protection

Implementing molecular marker technology in forage improvement

2003 ◽  
pp. 229-238
Author(s):  
M. Faville ◽  
B. Barrett ◽  
A. Griffiths ◽  
M. Schreiber ◽  
C. Mercer ◽  
...  
Keyword(s):  
Quantitative Trait Locus ◽  
Genetic Variation ◽  
White Clover ◽  
Simple Sequence Repeat ◽  
Sequence Repeat ◽  
Linkage Groups ◽  
Seedling Vigour ◽  
Genome Map ◽  
Trait Locus ◽  
Simple Sequence

Accelerated improvement of two cornerstones of New Zealand's pastoral industries, per ennial ryegrass (Lolium perenne L.) and white clover (Trifolium repens L.), may be realised through the application of markerassisted selection (MAS) strategies to enhance traditional plant breeding programmes. Genome maps constructed using molecular markers represent the enabling technology for such strategies and we have assembled maps for each species using EST-SSR markers - simple sequence repeat (SSR) markers developed from expressed sequence tags (ESTs) representing genes. A comprehensive map of the white clover genome has been completed, with 464 EST-SSR and genomic SSR marker loci spanning 1125 cM in total, distributed across 16 linkage groups. These have been further classified into eight pairs of linkage groups, representing contributions from the diploid progenitors of this tetraploid species. In perennial ryegrass a genome map based exclusively on EST-SSR loci was constructed, with 130 loci currently mapped to seven linkage groups and covering a distance of 391 cM. This map continues to be expanded with the addition of ESTSSR loci, and markers are being concurrently transferred to other populations segregating for economically significant traits. We have initiated gene discovery through quantitative trait locus (QTL) analysis in both species, and the efficacy of the white clover map for this purpose was demonstrated with the initial identification of multiple QTL controlling seed yield and seedling vigour. One QTL on linkage group D2 accounts for 25.9% of the genetic variation for seed yield, and a putative QTL accounting for 12.7% of the genetic variation for seedling vigour was detected on linkage group E1. The application of MAS to forage breeding based on recurrent selection is discussed. Keywords: genome map, marker-assisted selection, perennial ryegrass, QTL, quantitative trait locus, SSR, simple sequence repeat, white clover

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors

2005 ◽  
Author(s):  
M.L. Anderson ◽  
P. Tangyunyong ◽  
T.A. Hill ◽  
C.Y. Nakakura ◽  
T.J. Headley ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
New Product Development ◽  
Yield Enhancement ◽  
Product Development Process ◽  
Product Lines ◽  
Scanning Capacitance Microscopy ◽  
Transmission Electron ◽  
Complementary Techniques ◽  
Analytical Tools

Abstract By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Infrared Emission Spectroscopy as a Reliability Tool

1999 ◽  
Author(s):  
Q. Kim ◽  
S. Kayali
Keyword(s):  
Spatial Resolution ◽  
Emission Spectroscopy ◽  
Hot Spot ◽  
Cost Effective ◽  
Infrared Emission ◽  
Test System ◽  
Operating Conditions ◽  
Yield Enhancement ◽  
Infrared Emission Spectroscopy ◽  
Channel Temperature

Abstract In this paper, we report on a non-destructive technique, based on IR emission spectroscopy, for measuring the temperature of a hot spot in the gate channel of a GaAs metal/semiconductor field effect transistor (MESFET). A submicron-size He-Ne laser provides the local excitation of the gate channel and the emitted photons are collected by a spectrophotometer. Given the state of our experimental test system, we estimate a spectral resolution of approximately 0.1 Angstroms and a spatial resolution of approximately 0.9 μm, which is up to 100 times finer spatial resolution than can be obtained using the best available passive IR systems. The temperature resolution (<0.02 K/μm in our case) is dependent upon the spectrometer used and can be further improved. This novel technique can be used to estimate device lifetimes for critical applications and measure the channel temperature of devices under actual operating conditions. Another potential use is cost-effective prescreening for determining the 'hot spot' channel temperature of devices under normal operating conditions, which can further improve device design, yield enhancement, and reliable operation. Results are shown for both a powered and unpowered MESFET, demonstrating the strength of our infrared emission spectroscopy technique as a reliability tool.

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