scholarly journals Effect of Backgrinding Tape Lamination on Die Alignment

2020 ◽  
pp. 1-4
Author(s):  
Bryan Christian Bacquian ◽  
Frederick Ray Gomez
Keyword(s):  
Integrated Circuit ◽  
Growth And Development ◽  
Essential Role ◽  
Vertical Structure ◽  
Semiconductor Industry ◽  
Ic Design ◽  
Die Attach ◽  
Alignment Problem ◽  
Horizontal Pressure ◽  
Technical Challenges

The continuing growth and development on semiconductor package miniaturization have become a particular interest and focus semiconductor industry. The importance of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design with silicon die or the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the wafer preparation or pre-assembly. With the introduction of new wafer preparation technologies such as dicing before grinding and laser die attach film (DAF) cut, technical challenges were inevitable. The paper focused on the effect of backgrinding tape lamination on die alignment. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the die mis-alignment problem.  For future works, the configuration could be applied on wafers with similar technology and/or application.

scholarly journals Mitigating Wafer Edge Cut Defect through Tensionless Tape Lamination Technique

2020 ◽  
pp. 41-44
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Essential Role ◽  
Vertical Structure ◽  
Ic Design ◽  
Die Attach ◽  
Horizontal Pressure ◽  
Assembly Technology ◽  
Technical Challenges ◽  
Cutting Problem ◽  
Wafer Edge

Thinner and smaller packages require thinner vertical structure of the integrated circuit (IC) design with the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the pre-assembly or wafer preparation. With the introduction of new pre-assembly technology such as laser die attach film (DAF) cut and dicing before grinding, technical challenges were expected. The paper focused on eliminating the edge cutting issue by considering the appropriate taping lamination technique. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the edge cutting problem.  For future works, the configuration shared in this paper could be applied on wafers with comparable technology.

scholarly journals A Study of Wafer Backgrinding Tape Selection for SOI Wafers

2019 ◽  
pp. 1-6
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Vertical Structure ◽  
Semiconductor Industry ◽  
Critical Item ◽  
Silicon On Insulator ◽  
Ic Design ◽  
Semiconductor Packages ◽  
Ic Package ◽  
Step Type ◽  
Soi Technology

The continuous development and trends on thinner semiconductor packages have become the focus in the semiconductor industry. The necessity of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the backgrinding process, itself. Wafer warpage is one of the main concerns during the backgrinding process. Wafer warpage varies depending on the wafer backgrinding stress and backgrinding tape (hereinafter referred to as BG tape) tension. Hence, tension between the surface protective tape and the wafer should be considered an important and critical item to consider during BG tape selection. Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior backgrinding. Evaluating the effect of BG tape selection to eliminate such warpage is discussed on this paper.

scholarly journals Optimization for Die Attach Film Delamination on Nickel-Palladium-Gold Die Pad

2020 ◽  
pp. 1-6
Author(s):  
Michael D. Capili
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Research Work ◽  
Moisture Sensitivity ◽  
Die Attach ◽  
Sensitivity Level ◽  
Level 1 ◽  
Reliability Performance ◽  
Maximum Reliability ◽  
Robust Reliability

In the Semiconductor Industry, the delamination performance of integrated circuit packaging is being aggressively improved. However, this task is complicated and difficult, as the defective failure is highly dependent on the compatibility of the material characteristics that may affect the entire Integrated Circuit package system under certain stress levels, both mechanical and thermal. This research work aims to study Die Attach process optimization in DAF adhesive for Nickel-Palladium-Gold Die Pad leadframe to achieve maximum reliability performance under IPC / JEDEC Moisture Sensitivity Level 1 (MSL1) at 260°C reflow. Strategic optimization of the Die Attach process is needed to ensure robust reliability. And one of the solutions is to apply the Scrubbing method, which is a machine feature used at a constant temperature to aid in the wetting of adhesives and the removal of voids.

INTELLECTUAL CAPITAL AND PERFORMANCE IN THE SEMICONDUCTOR INDUSTRY

2019 ◽  
Vol 65 (05) ◽  
pp. 1323-1348
Author(s):  
KUO-CHENG KUO ◽  
WEN-MIN LU ◽  
GRACE TZU-YI CHANG
Keyword(s):  
Intellectual Capital ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Malmquist Productivity Index ◽  
Productivity Index ◽  
Efficient Production ◽  
Ic Design ◽  
Ic Packaging ◽  
And Performance ◽  
The Relationship

This paper researches a method of rating competitiveness involving the estimation of the performance of semiconductor firms through Malmquist productivity index (MPI) and metafrontier Malmquist productivity index (MMPI). Regressions are used to find the relationship between intellectual capital and performance. Overall, technological innovations contribute to the improvement in the integrated circuit (IC) design sub-industry while increases in efficient production allow the IC foundry sub-industry and the IC packaging and testing sub-industry to maintain position. The regression results show human capital was critical to technological innovation while relational capital was important to efficient production.

scholarly journals A Study of Vacuum Efficiency for Silicon on Insulator Wafers

2019 ◽  
pp. 1-6
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Vertical Structure ◽  
Silicon On Insulator ◽  
Major Contributor ◽  
Ic Design ◽  
Packaging Industry ◽  
Ic Package ◽  
Semiconductor Packaging ◽  
Step Type ◽  
Soi Technology

The development on thinner packages has become the trend and focus in semiconductor packaging industry. The necessity of thinner packages also entails a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the back grinding process, itself. Wafer warpage is one of the main concerns during the process. The effect of proper vacuuming will play major role in processing SOI wafers. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poorer grinding and worst broken wafer.  Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior back grinding. Evaluating the effect of vacuum efficiency to eliminate such warpage is discussed on this technical paper.

scholarly journals Package Design Optimization with Reliability Test Verification for Reduction of Voids and Delamination

2018 ◽  
Vol 6 (6) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
Rammil A. Seguido
Keyword(s):  
Design Optimization ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Optimization Approach ◽  
Multiple Channels ◽  
Package Design ◽  
Die Attach ◽  
Semiconductor Packages ◽  
To Come ◽  
Test Verification

Package down-scaling or miniaturization has become the trend in semiconductor industry, with smaller and thinner package being the prime objective.  Stacked dice process in semiconductor packages is now also becoming popular as semiconductor industries try to come up with products that offer multiple channels in a small IC (integrated circuit) package.  However, as different dice are brought together, several challenges have to be overcome in terms of package design and assembly.This technical paper specifically considers the challenges encountered in the development of a compact and thinner package that incorporates multiple or stacked dice in one.  For the case of this paper, Die1 is smaller than Die2 and must be the first one to be die bonded, making the internal construction an unbalanced stacked dice.  Normally, stacked dice is in pyramid layout, wherein a single large die supports smaller top die.  Nevertheless, success is measured when there is a solution to control die attach voids and eliminate or significantly minimize delamination for unbalanced stacked dice as mentioned.  Ultimately, the paper presents the understanding of the factors involved and the package design optimization approach used to produce a successful unbalanced stacked die in a thin package using thin substrate.

Pre-Evaluating the Technical Efficiency Gains from Potential Mergers and Acquisitions in the IC Design Industry

2020 ◽  
Vol 19 (02) ◽  
pp. 525-559
Author(s):  
Ying Li ◽  
Yung-Ho Chiu ◽  
Tai-Yu Lin ◽  
Tzu-Han Chang
Keyword(s):  
Mergers And Acquisitions ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Past Research ◽  
Global Competition ◽  
Efficiency Gains ◽  
Ic Design ◽  
Industry Growth ◽  
Competitive Edge ◽  
Management Efficiency

Increased global competition has led to a slowdown in Taiwan’s domestic semiconductor industry growth, which has resulted in many semiconductor companies reducing their investments and or seeking mergers and acquisitions (M & As) to increase market power, expand their business territories or increase their competitive edge. However, as there is general uncertainty regarding the efficiencies to be gained from these M & As, there has been an increase in M & A supervision. While past research has explored company operations and management efficiency after mergers, there has been less focus on potential mergers. Therefore, this study used a resample slacks-based measure (RSBM) and merger potential gains models to evaluate potential merger efficiency gains. Data on 29 Taiwanese-listed integrated circuit (IC) design industry firms were collected to evaluate the efficiency of potential M & As, from which it was found that the potential M & As efficiencies had positive and negative values, indicating that efficiency gains were not guaranteed. A positive value was found for a potential M & A between MTK & NOVATEK and MTK & DAVICOM, which meant that a potential M & A would increase operating efficiencies and reduce costs.

scholarly journals Laser DAF Cut Augmentation for Thin Wafers

2020 ◽  
pp. 24-31
Author(s):  
Bryan Christian Bacquian ◽  
Frederick Ray Gomez
Keyword(s):  
Integrated Circuit ◽  
New Technologies ◽  
Process Development ◽  
Semiconductor Industry ◽  
Die Attach ◽  
Critical Characteristics ◽  
Wafer Processing ◽  
Material Solution ◽  
Different Characteristics ◽  
Sawing Process

The semiconductor industry is becoming more inclined to thinner integrated circuit (IC) packages. Thinner packages with thin wafer or die prefer the die attach film (DAF) technology as the die adhesive material solution. As the wafer goes thinner, it becomes more of a challenge in process development, especially during its assembly preparatory stages. As the dies become smaller and thinner, wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality. New technologies were developed and introduced in the industry and one of this is the laser die attach film (DAF) cutting. The method was developed together with dies before grinding (DBG) as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw. This paper discusses the laser DAF cut development covering the design of experiments (DOE) to understand the different characteristics of laser DAF solution. Validations are made through actual simulation and wafer processing. The paper also covers the interaction of different DAF thicknesses and parameters in order to define the critical characteristics in achieving optimal DAF cutting process responses.

The Vertical Disintegration of Taiwan's Semiconductor Industries: Price and Non-Price Factors

2004 ◽  
Vol 07 (04) ◽  
pp. 547-569 ◽  
Author(s):  
Shiu-Wan Hung ◽  
Chyan Yang ◽  
Cheng-Few Lee
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Market Price ◽  
Government Support ◽  
Ic Design ◽  
Vertical Disintegration ◽  
Ic Manufacturing ◽  
The World ◽  
Future Challenges

Taiwan's semiconductor industry has been prominent and ranks number four in the world. The vertical disintegration model of Taiwan's semiconductor is a very unique one among the integrated circuit industries around the world. The objective of this paper is to study the vertical disintegration management of Taiwan's semiconductor industries. A price model which there are both integrated (IDM) and unintegrated (IC foundry and IC fabless separated) firms was presented. A vertical disintegration model in which there is a Cournot–Nash equilibrium at both stages of production, upstream (IC design) and downstream (IC fabrication), has been proposed to explain analytically the market price changes subjected to vertical disintegration. It was suggested that the market price of the integrated circuit decreases if the numbers of IC fabless firms are more than half of the total IC firms and are more than the numbers of IC manufacturing firms. In addition, five non-price factors leading to the vertical disintegration of Taiwan's semiconductor industries have been proposed: (1) industrial localization and cluster, (2) fast changes of technology, (3) significant increase of development cost, (4) emergence of IC fabless, and (5) government support. By spinning off the equipment division which needs a high capital, the semiconductor company can actually make profits by concentrating more on the increasingly complex integrated circuit designs. The disintegrated foundry companies can provide advantages of more specialty, higher quality, lower cycle time and good cooperation relations for the IC fabless firms. The vertical disintegration of integrated circuits is expected to be the trend for future for semiconductor manufacturing. In addition, the future challenges and directions of Taiwan's semiconductor industries were also discussed.

Plant hormones, plant growth regulators

2014 ◽  
Vol 155 (26) ◽  
pp. 1011-1018 ◽  
Author(s):  
György Végvári ◽  
Edina Vidéki
Keyword(s):  
Nervous System ◽  
Growth And Development ◽  
Large Scale ◽  
Essential Role ◽  
Higher Plants ◽  
Structure And Function ◽  
Wide Sense ◽  
Large Scale Integration ◽  
Scale Integration ◽  
And Function

Plants seem to be rather defenceless, they are unable to do motion, have no nervous system or immune system unlike animals. Besides this, plants do have hormones, though these substances are produced not in glands. In view of their complexity they lagged behind animals, however, plant organisms show large scale integration in their structure and function. In higher plants, such as in animals, the intercellular communication is fulfilled through chemical messengers. These specific compounds in plants are called phytohormones, or in a wide sense, bioregulators. Even a small quantity of these endogenous organic compounds are able to regulate the operation, growth and development of higher plants, and keep the connection between cells, tissues and synergy beween organs. Since they do not have nervous and immume systems, phytohormones play essential role in plants’ life. Orv. Hetil., 2014, 155(26), 1011–1018.

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