scholarly journals A Study of Vacuum Efficiency for Silicon on Insulator Wafers

2019 ◽  
pp. 1-6
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Vertical Structure ◽  
Silicon On Insulator ◽  
Major Contributor ◽  
Ic Design ◽  
Packaging Industry ◽  
Ic Package ◽  
Semiconductor Packaging ◽  
Step Type ◽  
Soi Technology

The development on thinner packages has become the trend and focus in semiconductor packaging industry. The necessity of thinner packages also entails a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the back grinding process, itself. Wafer warpage is one of the main concerns during the process. The effect of proper vacuuming will play major role in processing SOI wafers. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poorer grinding and worst broken wafer.  Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior back grinding. Evaluating the effect of vacuum efficiency to eliminate such warpage is discussed on this technical paper.

scholarly journals A Study of Wafer Backgrinding Tape Selection for SOI Wafers

2019 ◽  
pp. 1-6
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Vertical Structure ◽  
Semiconductor Industry ◽  
Critical Item ◽  
Silicon On Insulator ◽  
Ic Design ◽  
Semiconductor Packages ◽  
Ic Package ◽  
Step Type ◽  
Soi Technology

The continuous development and trends on thinner semiconductor packages have become the focus in the semiconductor industry. The necessity of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the backgrinding process, itself. Wafer warpage is one of the main concerns during the backgrinding process. Wafer warpage varies depending on the wafer backgrinding stress and backgrinding tape (hereinafter referred to as BG tape) tension. Hence, tension between the surface protective tape and the wafer should be considered an important and critical item to consider during BG tape selection. Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior backgrinding. Evaluating the effect of BG tape selection to eliminate such warpage is discussed on this paper.

scholarly journals A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

2020 ◽  
pp. 51-57
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Silicon Wafer ◽  
Semiconductor Manufacturing ◽  
Manufacturing Industry ◽  
Vertical Structure ◽  
Silicon On Insulator ◽  
Major Contributor ◽  
Electronic Package ◽  
Semiconductor Electronic ◽  
Soi Technology ◽  
Comprehensive Study

The relentless advancement and trends on thinner packages have become the focus in the semiconductor manufacturing industry. The requirement of thinner packages also demands a thinner vertical structure of the semiconductor electronic design. As a major contributor on the vertical structure of the electronic package, die or wafer is also essential to go thinner. As the wafer becomes thinner, various problems may occur during transport and even the backgrinding process itself. Wafer warpage is one of the main concerns during the wafer backgrinding process. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poor grinding and broken wafer. Wafer backgrinding stress and backgrinding tape tension also contribute to the effect on wafer warpage. Challenges exist in processing different silicon wafer technology, particularly the silicon-on-insulator (SOI) technology. Evaluating the effect of backgrinding tape selection and vacuum efficiency to eliminate such warpage is presented in this paper.

Silicon-on-lnsulator Technology: Past Achievements and Future Prospects

MRS Bulletin ◽  
1998 ◽  
Vol 23 (12) ◽  
pp. 16-19 ◽  
Author(s):  
Jean-Pierre Colinge
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Current Gain ◽  
Silicon Devices ◽  
Microelectronics Industry ◽  
Radiation Hard ◽  
Soi Technology

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.

scholarly journals Mitigating Wafer Edge Cut Defect through Tensionless Tape Lamination Technique

2020 ◽  
pp. 41-44
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Essential Role ◽  
Vertical Structure ◽  
Ic Design ◽  
Die Attach ◽  
Horizontal Pressure ◽  
Assembly Technology ◽  
Technical Challenges ◽  
Cutting Problem ◽  
Wafer Edge

Thinner and smaller packages require thinner vertical structure of the integrated circuit (IC) design with the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the pre-assembly or wafer preparation. With the introduction of new pre-assembly technology such as laser die attach film (DAF) cut and dicing before grinding, technical challenges were expected. The paper focused on eliminating the edge cutting issue by considering the appropriate taping lamination technique. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the edge cutting problem.  For future works, the configuration shared in this paper could be applied on wafers with comparable technology.

scholarly journals Effect of Backgrinding Tape Lamination on Die Alignment

2020 ◽  
pp. 1-4
Author(s):  
Bryan Christian Bacquian ◽  
Frederick Ray Gomez
Keyword(s):  
Integrated Circuit ◽  
Growth And Development ◽  
Essential Role ◽  
Vertical Structure ◽  
Semiconductor Industry ◽  
Ic Design ◽  
Die Attach ◽  
Alignment Problem ◽  
Horizontal Pressure ◽  
Technical Challenges

The continuing growth and development on semiconductor package miniaturization have become a particular interest and focus semiconductor industry. The importance of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design with silicon die or the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the wafer preparation or pre-assembly. With the introduction of new wafer preparation technologies such as dicing before grinding and laser die attach film (DAF) cut, technical challenges were inevitable. The paper focused on the effect of backgrinding tape lamination on die alignment. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the die mis-alignment problem.  For future works, the configuration could be applied on wafers with similar technology and/or application.

Acoustic microscopy techniques for the inspection of integrated circuit devices and packages

1992 ◽  
Vol 50 (2) ◽  
pp. 966-967
Author(s):  
Thomas M. Moore
Keyword(s):  
Integrated Circuit ◽  
Acoustic Microscopy ◽  
Hybrid Technique ◽  
Frequency Scanning ◽  
Ic Packaging ◽  
Ic Package ◽  
Microscopy Techniques ◽  
Ic Package Inspection ◽  
Pulse Echo ◽  
Scanning Acoustic Microscope

In the last decade, a variety of characterization techniques based on acoustic phenomena have come into widespread use. Characteristics of matter waves such as their ability to penetrate optically opaque solids and produce image contrast based on acoustic impedance differences have made these techniques attractive to semiconductor and integrated circuit (IC) packaging researchers.These techniques can be divided into two groups. The first group includes techniques primarily applied to IC package inspection which take advantage of the ability of ultrasound to penetrate deeply and nondestructively through optically opaque solids. C-mode Acoustic Microscopy (C-AM) is a recently developed hybrid technique which combines the narrow-band pulse-echo piezotransducers of conventional C-scan recording with the precision scanning and sophisticated signal analysis capabilities normally associated with the high frequency Scanning Acoustic Microscope (SAM). A single piezotransducer is scanned over the sample and both transmits acoustic pulses into the sample and receives acoustic echo signals from the sample.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology

2014 ◽  
Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Cost Effective ◽  
Tetraethyl Orthosilicate ◽  
Ic Design ◽  
Advance Technology ◽  
Defect Identification ◽  
Technology Scaling ◽  
And Function ◽  
Metal Layers

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Design and characteristics of reflectivity tunable mirror with MZI and loop waveguide on SOI

2021 ◽  
Author(s):  
Yutaka Makihara ◽  
Moataz Eissa ◽  
Tomohiro AMEMIYA ◽  
Nobuhiko Nishiyama
Keyword(s):  
Phase Shift ◽  
Coupling Coefficient ◽  
Integrated Circuit ◽  
Silicon Photonics ◽  
Silicon On Insulator ◽  
Zehnder Interferometer ◽  
Directional Couplers ◽  
Photonic Integrated Circuit ◽  
Active Elements ◽  
Measurement Results

Abstract To achieve a reconfigurable photonic integrated circuit with active elements, we proposed a reflectivity tunable mirror constructed using a Mach–Zehnder interferometer (MZI) with a micro heater and loop waveguide on a silicon photonics platform. In this paper, the principle of the operation, design, fabrication, and measurement results of the mirror are presented. In theory, the phase shift dependence of the mirror relies on the coupling coefficient of the directional couplers of the MZI. When the coupling coefficient κ2 was 0.5 and 0.15, the reflection could be turned on and off with a phase shift of π/2 and π, respectively. The reflection power of the fabricated mirror on the silicon on insulator (SOI) substrate was changed by more than 20 dB by a phase shift. In addition, it was demonstrated that the phase shift dependence of the mirror changes with the coupling coefficient of the fabricated devices.

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