High polarization and wake-up free ferroelectric characteristics in ultrathin Hf0.5Zr0.5O2 devices by control of oxygen-deficient layer

2021 ◽  
Author(s):  
MANOJ YADAV ◽  
Alireza Kashir ◽  
Seungyeol Oh ◽  
REVANNATH DNYANDEO NIKAM ◽  
Hyungwoo Kim ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Ferroelectric Properties ◽  
Atomic Layer ◽  
Layer Formation ◽  
Device Structure ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Transmission Electron ◽  
Memory Applications

Abstract The formation of an interfacial layer is believed to affect the ferroelectric properties in HfO2 based ferroelectric devices. The atomic layer deposited devices continue suffering from a poor bottom interfacial condition, since the formation of bottom interface is severely affected by atomic layer deposition (ALD) and annealing process. Herein, the formation of bottom interfacial layer was controlled through deposition of different bottom electrodes (BE) in device structure W/HZO/BE. The transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) analyses done on devices W/HZO/W and W/HZO/IrOx suggest the strong effect of IrOx in controlling bottom interfacial layer formation while W/HZO/W badly suffers from interfacial layer formation. W/HZO/IrOx devices show high remnant polarization (2Pr) ~ 53 µC/cm2, wake-up free endurance cycling characteristics, low leakage current with demonstration of low annealing temperature requirement as low as 350°C, valuable for BEOL integration. Further, sub-5 nm HZO thicknesses-based W/HZO/IrOx devices demonstrate high 2Pr and wake-up free ferroelectric characteristics, which can be promising for low power and high-density memory applications. 2.2 nm, 3 nm, and 4 nm HZO based W/HZO/IrOx devices show 2Pr values 13.54, 22.4, 38.23 µC/cm2 at 4 MV/cm and 19.96, 30.17, 48.34 µC/cm2 at 5 MV/cm, respectively, with demonstration of wake-up free ferroelectric characteristics.

An optimized process for fabrication of SrBi2Ta2O9 thin films using a novel chemical solution deposition technique

1999 ◽  
Vol 14 (11) ◽  
pp. 4395-4401 ◽  
Author(s):  
Seung-Hyun Kim ◽  
D. J. Kim ◽  
K. M. Lee ◽  
M. Park ◽  
A. I. Kingon ◽  
...  
Keyword(s):  
Thin Films ◽  
Chemical Solution Deposition ◽  
Low Voltage ◽  
Ferroelectric Properties ◽  
Chemical Solution ◽  
Solution Deposition ◽  
Chemical Solution Deposition Method ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Voltage Saturation

Ferroelectric SrBi2Ta2O9 (SBT) thin films on Pt/ZrO2/SiO2/Si were successfully prepared by using an alkanolamine-modified chemical solution deposition method. It was observed that alkanolamine provided stability to the SBT solution by retarding the hydrolysis and condensation rates. The crystallinity and the microstructure of the SBT thin films improved with increasing annealing temperature and were strongly correlated with the ferroelectric properties of the SBT thin films. The films annealed at 800 °C exhibited low leakage current density, low voltage saturation, high remanent polarization, and good fatigue characteristics at least up to 1010 switching cycles, indicating favorable behavior for memory applications.

High-Temperature Trench Capacitors, Using Thin-Film ALD Dielectrics

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000130-000133 ◽  
Author(s):  
Dorothee Dietz ◽  
Yusuf Celik ◽  
Andreas Goehlich ◽  
Holger Vogt ◽  
Holger Kappert
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Automobile Industry ◽  
Elevated Temperatures ◽  
Atomic Layer ◽  
Operating Voltage ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Layer Deposition ◽  
Soft Breakdown

High-temperature passive electronic becomes more and more important, e.g. in the field of deep drilling, aerospace or in automobile industry. For these applications, capacitors are needed, which are able to withstand temperatures up to 300 °C, which exhibit a low leakage current at elevated temperatures, a breakdown voltage above the intended operating voltage and a high capacitive density value. In this paper, investigations of 3D-integration and atomic layer deposition (ALD) techniques to achieve these features are presented. A highly n-doped Si-substrate acts as a bottom electrode. Medium- and high-k dielectrics represent the insulator and the upper electrode consists of Ru, TiN or TiAlCN. The materials can be used at elevated temperatures. At room temperature, the leakage current is less than 10 pA/mm2 without showing a soft-breakdown up to ± 15 V, indicating the absence of Fowler-Nordheim tunneling. At 300 °C and at 3 V the leakage current amounts about 1 nA/mm2 and at 5 V a soft-breakdown is detected.

scholarly journals Characterization of Electrical Traps Formed in Al2O3 under Various ALD Conditions

Materials ◽  
2020 ◽  
Vol 13 (24) ◽  
pp. 5809
Author(s):  
Md. Mamunur Rahman ◽  
Ki-Yong Shin ◽  
Tae-Woo Kim
Keyword(s):  
Leakage Current ◽  
Deposition Temperature ◽  
Fundamental Property ◽  
Frequency Dispersion ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Semiconductor Interface ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Deposited Film

Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.

Interfacial Characteristics for LaAlO3 Gate Dielectric on S Passivated GaAs Substrate

2012 ◽  
Vol 629 ◽  
pp. 127-130
Author(s):  
Ting Ting Jia ◽  
Xing Hong Cheng ◽  
Duo Cao ◽  
Da Wei Xu ◽  
Chao Xia ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Interface Morphology ◽  
X Ray ◽  
Transmission Electron ◽  
Layer Deposition ◽  
Chemical Bonding State ◽  
Capacitance Voltage ◽  
Sulfur Passivation

In this work, we present the results of an investigation into the effectiveness of varying ammonium sulphide (NH4)2S concentrations in the passivation of n-type GaAs. Samples were degreased and immersed in aqueous (NH4)2S solutions of concentrations 22% and 10%for 10 min at 295 K, immediately prior to plasma enhanced atomic layer deposition of LaAlO3. The chemical bonding state of (NH4)2S treated GaAs surface were investigated by X-ray photoelectron spectroscopy (XPS), which indicate that Sulfur passivation can reduce intrerfacial GaAs-oxide formation. Transmission electron microscopy (TEM) was implemented to characterize the interface morphology. Finally, capacitance-voltage (C-V) and leakage current density-voltage (J-V) measurement were used to characterize the electrical properties of LaAlO3 films.

The Interface Properties of La2O3/GaAs System by Surface Passivation

2012 ◽  
Vol 557-559 ◽  
pp. 1815-1818 ◽  
Author(s):  
Ting Ting Jia ◽  
Xing Hong Cheng ◽  
Duo Cao ◽  
Da Wei Xu ◽  
You Wei Zhang ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Surface Passivation ◽  
Gate Dielectric ◽  
Surface Preparation ◽  
Atomic Layer ◽  
Native Oxide ◽  
Atomic Force ◽  
Transmission Electron ◽  
Layer Deposition

In this work, La2O3 gate dielectric film was deposited by plasma enhanced atomic layer deposition. we investigate the effect of surface preparation of GaAs substrate, for example, native oxide, S-passivation, and NH3 plasma in situ treatment. The interfacial reaction mechanisms of La2O3 on GaAs is studied by means of X-ray photoelectron spectroscopy(XPS), high-resolution transmission electron microscopy(HRTEM) and atomic force microscope (AFM). As-O bonding is found to get effectively suppressed in the sample GaAs structures with both S-passivation and NH3 plasma surface treatments.

Correlation of Phase Segregation and Electrical Properties of Low-Power MOSFETs with Hf-based Silicate Gate Dielectric Layers and TaN Metal Gates

2006 ◽  
Vol 917 ◽  
Author(s):  
Jasmine Petry ◽  
Chris Rittersma ◽  
Georgios Vellianitis ◽  
Vincent Cosnier ◽  
Thierry Conard ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Phase Segregation ◽  
Atomic Layer ◽  
Gate Leakage ◽  
Electrical Measurements ◽  
Metal Gates ◽  
Fourier Transformed Infrared Spectroscopy ◽  
Transmission Electron ◽  
Layer Deposition

AbstractThe need for nitridation of Hf silicate is controversial. On one hand, it has not been proven that the nitridation is mandatory to have working devices and on the other hand, it is known to increase the charge density. In this paper, we present a detailed comprehensive study of the role and the need for nitridation of Hf-based silicates deposited by Atomic Layer Deposition (ALD). The results are based on a correlation of Fourier-Transformed Infrared Spectroscopy (FT-IR), X-ray Photoelectron Spectroscopy (XPS), High-resolution Transmission Electron Microscopy (HR-TEM) and electrical measurements (gate leakage and mobility).It was observed that the phase segregation in gate dielectrics is not detrimental for the gate leakage density at room temperature. However, the leakage current is significantly increased at higher temperature. The incorporation of nitrogen was either done by NH3 anneal (at 800C) or by Decoupled Plasma Nitridation (DPN – 25.9kJ). While the DPN or NH3 anneal prevent phase segregation for 50% Hf silicate, only the NH3 anneal helps prevent the phase segregation of Hf-rich silicate. Furthermore, the NH3 anneal increases the interfacial thickness, which produces a very low gate leakage with only 10% loss in mobility at high field. Interestingly, DPN followed by O2 anneal leads to an advantageous phase segregation of the Hf-rich silicate by transforming the silicate in a HfO2/SiO2-like stack.As a conclusion, not only the phase segregation of the silicate does not always lead to shorted devices, but it can be beneficial in terms of mobility. However, the phase segregation seems to be responsible for an enlarged trap-assisted conduction mechanism at high temperature. But even if the 50% Hf silicates non-nitrided leads to working devices, the incorporation of nitrogen in the stack improves the Jg/CET trends and is therefore beneficial.

Low leakage current and good ferroelectric properties of SrBi2(Ta0.7Nb0.3)2O9–Bi3TiTaO9 solid solution thin film

2001 ◽  
Vol 79 (13) ◽  
pp. 2067-2069 ◽  
Author(s):  
Masatoshi Mitsuya ◽  
Norimasa Nukaga ◽  
Takayuki Watanabe ◽  
Hiroshi Funakubo ◽  
Keisuke Saito ◽  
...  
Keyword(s):  
Thin Film ◽  
Solid Solution ◽  
Leakage Current ◽  
Ferroelectric Properties ◽  
Low Leakage ◽  
Low Leakage Current

Comparative Study of Electrical and Microstructural Properties of 4H-SiC MOSFETs

2012 ◽  
Vol 717-720 ◽  
pp. 437-440 ◽  
Author(s):  
Christian Strenger ◽  
Volker Haeublein ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Heiner Ryssel ◽  
...  
Keyword(s):  
Electron Mobility ◽  
Interfacial Layer ◽  
Chemical Properties ◽  
Microstructural Properties ◽  
Layer Formation ◽  
Carbon Distribution ◽  
Transmission Electron ◽  
Inversion Channel ◽  
P Type ◽  
And Chemical Properties

N-channel MOSFETs were manufactured on p-type and on p-implanted, n-type 4H-SiC substrates. The electron mobility in the inversion channel was measured to be correlated with the structural and chemical properties determined by transmission electron microscopy. With regard to what was previously discussed in the literature, interfacial layer formation and carbon distribution across the SiC/SiO2 interface were considered in relation with the measured Hall electron mobility.

STRUCTURAL AND DIELECTRIC PROPERTIES OF Ba0.5Sr0.5TiO3 THIN FILMS GROWN ON LAO WITH HOMO-EPITAXIAL LAYER FOR TUNABLE APPLICATIONS

2004 ◽  
Vol 18 (15) ◽  
pp. 2153-2168 ◽  
Author(s):  
M. CHANDRA SEKHAR
Keyword(s):  
Dielectric Constant ◽  
Dielectric Properties ◽  
Interfacial Layer ◽  
Ferroelectric Properties ◽  
Buffer Layers ◽  
High Tunability ◽  
Low Leakage ◽  
Structural Growth ◽  
Bst Films ◽  
Dielectric Devices

The epitaxial, single phase (100) Ba 0.5 Sr 0.5 TiO 3 (BST) films with thin interfacial layer of BST (x=0.4) were deposited on LAO (100) substrates using Pulse Laser Deposition (PLD). These films were characterized in terms of their phase formation and structural growth characteristics using X-ray diffraction and Atomic Force Microscopy respectively. The dielectric properties are strongly affected by the substrate type, post deposition annealing time, and temperature. In order to verify all these properties, thin interfacial-buffer layers of BST (10, 20, 50 nm) were introduced to relieve the stress induced between the film and the substrate. The variations of dielectric constant and ferroelectric properties of as deposited films are discussed in detail. The high tunability, low dielectric loss and low leakage current of these films make them attractive candidates for fabricating tunable dielectric devices. The observed dielectric properties of the BST-films are attributed to homo-epitaxial interfacial layer, which is responsible for the increase in the dielectric constant and tunability.

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