scholarly journals An Efficient and Flexible Window Function for Memristor Model and its Analog Circuit Application

2021 ◽  
Author(s):  
chandra prakash singh
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Boundary Effect ◽  
Window Function ◽  
Linear Drift ◽  
Programmable Analog ◽  
Pinched Hysteresis Loop ◽  
Resistance State ◽  
Function Discontinuity ◽  
New Applications

Abstract The memristor is a nanostructure resistive tuning two terminal novel electronics device that has been widely explored in the area of neuromorphic computing systems, memories, digital circuits, analog circuits and many more new applications. In this article an efficient and flexible window function is presented for linear drift memristor model. Propose window function provides a unique feature (controllable window function discontinuity) to linear drift memristor model by which DPHL (Distorted Pinched Hysteresis Loop) problem is resolved and also improved the programming resistance state of the memristor. Five control parameters are introduced in the presented window function, in order to fix the pre-existing problem (like boundary effect, boundary lock and inflexibility) and make it more flexible. The programmable analog gain amplifier circuit is ultimately executed to instantiate the utilization of evolved memristor model.

scholarly journals Analog Reconfigurable Circuits

2014 ◽  
Vol 60 (1) ◽  
pp. 8-19 ◽  
Author(s):  
Andrzej Malcher ◽  
Piotr Falkowski
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Dynamic Reconfiguration ◽  
Reconfigurable Circuits ◽  
Analog Electronics ◽  
Programmable Analog ◽  
Field Programmable ◽  
Field Programmable Analog Arrays ◽  
Analog Arrays

Abstract The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA

Analog Circuit Failure Analysis Using Time-Resolved Emission

2005 ◽  
Author(s):  
B.J. Cain ◽  
G.L. Woods ◽  
A. Syed ◽  
R. Herlein ◽  
Toshihiro Nomura
Keyword(s):  
Analog Circuits ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Photon Emission ◽  
Nonlinear Process ◽  
Time Resolved ◽  
Non Invasive ◽  
Highly Nonlinear ◽  
Excellent Spatial Resolution ◽  
5 Ghz

Abstract Time-Resolved Emission (TRE) is a popular technique for non-invasive acquisition of time-domain waveforms from active nodes through the backside of an integrated circuit. [1] State-of-the art TRE systems offer high bandwidths (> 5 GHz), excellent spatial resolution (0.25um), and complete visibility of all nodes on the chip. TRE waveforms are typically used for detecting incorrect signal levels, race conditions, and/or timing faults with resolution of a few ps. However, extracting the exact voltage behavior from a TRE waveform is usually difficult because dynamic photon emission is a highly nonlinear process. This has limited the perceived utility of TRE in diagnosing analog circuits. In this paper, we demonstrate extraction of voltage waveforms in passing and failing conditions from a small-swing, differential logic circuit. The voltage waveforms obtained were crucial in corroborating a theory for some failures inside an 0.18um ASIC.

Laser Based Analysis on Analog Circuits with Feedback Loops and a Case Study

2006 ◽  
Author(s):  
Fubin Zhang ◽  
David Maxwell
Keyword(s):  
Success Rate ◽  
High Resistance ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Feedback Loops ◽  
Induced Voltage ◽  
Analog Device ◽  
Analog Ic ◽  
Successful Isolation

Abstract Based on the understanding of laser based techniques’ physics theory and the topology/structure of analog circuit systems with feedback loops, the propagation of laser induced voltage/current alteration inside the analog IC is evaluated. A setup connection scheme is proposed to monitor this voltage/current alteration to achieve a better success rate in finding the fail site or defect. Finally, a case of successful isolation of a high resistance via on an analog device is presented.

Concepts for In Situ Diagnostics in Analog Microelectronic Circuits

2007 ◽  
Author(s):  
Ted Kolasa ◽  
Alfredo Mendoza
Keyword(s):  
Analog Circuits ◽  
System Architecture ◽  
Analog Circuit ◽  
Fault Localization ◽  
Diagnostic System ◽  
Diagnostic Capability ◽  
Common Signal ◽  
Diagnostic Capabilities ◽  
In Situ Diagnostics

Abstract Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.

scholarly journals A Neural Network Classifier with Multi-Valued Neurons for Analog Circuit Fault Diagnosis

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 349
Author(s):  
Igor Aizenberg ◽  
Riccardo Belardi ◽  
Marco Bindi ◽  
Francesco Grasso ◽  
Stefano Manetti ◽  
...  
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Machine Learning Techniques ◽  
Rigorous Approach ◽  
Testability Analysis ◽  
Learning Techniques ◽  
Fabrication Tolerances ◽  
Circuit Fault Diagnosis ◽  
Faulty Component ◽  
Ambiguity Groups

In this paper, we present a new method designed to recognize single parametric faults in analog circuits. The technique follows a rigorous approach constituted by three sequential steps: calculating the testability and extracting the ambiguity groups of the circuit under test (CUT); localizing the failure and putting it in the correct fault class (FC) via multi-frequency measurements or simulations; and (optional) estimating the value of the faulty component. The fabrication tolerances of the healthy components are taken into account in every step of the procedure. The work combines machine learning techniques, used for classification and approximation, with testability analysis procedures for analog circuits.

scholarly journals Analog Circuit Design Automation Tool Using Genetic Algorithms

1970 ◽  
Vol 1 (1) ◽  
Author(s):  
Y. M. A. Khalifa ◽  
D. H. Horrocks
Keyword(s):  
Genetic Algorithms ◽  
Circuit Design ◽  
Analog Circuits ◽  
Computer Aided Design ◽  
Degrees Of Freedom ◽  
Analog Circuit ◽  
Search Space ◽  
Design Stage ◽  
Specific Frequency ◽  
Aided Design

An investigation into the application of Genetic Algorithms (GA) for the design of electronic analog circuits is presented in this paper. In this paper an investigation of the use of genetic algorithms into the problem of analog circuits design is presented. In a single design stage, circuits are produced that satisfy specific frequency response specifications using circuit structures that are unrestricted and with component values that are chosen from a set of preferred values. The extra degrees of freedom resulting from unbounded circuit structures create a huge search space. It is shown in this paper that Genetic Algorithms can be successfully used to search this space. The application chosen is a LC all pass ladder filter circuit design.Key Words: Computer-Aided Design, Analog Circuits, Artificial Intelligence.

Process voltage temperature analysis of MOS based balanced pseudo-resistors for biomedical analog circuit applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Kulbhushan Sharma ◽  
Anisha Pathania ◽  
Jaya Madan ◽  
Rahul Pandey ◽  
Rajnish Sharma
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Common Mode ◽  
Temperature Variations ◽  
Time Constants ◽  
Content Type ◽  
Common Mode Voltage ◽  
Design Techniques

Purpose Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications. Design/methodology/approach In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process. Findings The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations. Research limitations/implications Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits. Social implications The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics. Originality/value The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

scholarly journals FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Ravindra Singh Kushwah ◽  
Shyam Akashe
Keyword(s):  
Analog Circuits ◽  
High Performance ◽  
Analog Circuit ◽  
Schmitt Trigger ◽  
Low Noise ◽  
Operational Transconductance Amplifier ◽  
Back Gate ◽  
Amplifier Circuit ◽  
Tunable Circuits ◽  
Transconductance Amplifier

We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

Recognition and Diagnosis of the Incipient Faults in Analog Circuit Using Improved HMM

2012 ◽  
Vol 588-589 ◽  
pp. 843-846
Author(s):  
Ji Jun Zhang ◽  
Deng Wu Ma ◽  
Lin Wang
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
State Transition ◽  
Transition Probability ◽  
Control Factor ◽  
Time Varying ◽  
State Transition Probability ◽  
Fault Recognition ◽  
Initial Stage ◽  
Incipient Faults

Due to the uncertainties that exist in the running of the analog circuits, the traditional hidden Markov model (HMM) approach is improved through replacing the state transition probability (STP) matrix of the traditional model by time-varying one. An updating control factor is introduced for avoiding the excess updating of the STP in the initial stage of each state. The experimental results indicate that the improved HMM has better fault recognition and diagnosis capability.

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