Shear performance of microscale ball grid array structure Cu(Ni)/Sn–3.0Ag–0.5Cu/Cu(Ni) solder joints at low temperatures

2022 ◽  
pp. 103149
Author(s):  
Wangyun Li ◽  
Jun Gui ◽  
Hongbo Qin ◽  
Daoguo Yang
Crystals ◽  
2022 ◽  
Vol 12 (1) ◽  
pp. 85
Author(s):  
Bo Wang ◽  
Wangyun Li ◽  
Kailin Pan

The shear performance and fracture behavior of microscale ball grid array structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints with increasing electric current density (from 1.0 × 103 to 6.0 × 103 A/cm2) at various test temperatures (25 °C, 55 °C, 85 °C, 115 °C, 145 °C, and 175 °C) were investigated systematically. Shear strength increases initially, then decreases with increasing current density at a test temperature of no more than 85 °C; the enhancement effect of current stressing on shear strength decreases and finally diminishes with increasing test temperatures. These changes are mainly due to the counteraction of the athermal effect of current stressing and Joule heating. After decoupling and quantifying the contribution of the athermal effect to the shear strength of solder joints, the results show that the influence of the athermal effect presents a transition from an enhancement state to a deterioration state with increasing current density, and the critical current density for the transition decreases with increasing test temperatures. Joule heating is always in a deterioration state on the shear strength of solder joints, which gradually becomes the dominant factor with increasing test temperatures and current density. In addition, the fracture location changes from the solder matrix to the interface between the solder matrix and the intermetallic compound (IMC) layer (the solder/IMC layer interface) with increasing current density, showing a ductile-to-brittle transition. The interfacial fracture is triggered by current crowding at the groove of the IMC layer and driven by mismatch strain at the solder/IMC layer interface, and the critical current density for the occurrence of interfacial fracture decreases with increasing test temperatures.


Author(s):  
Tae-Yong Park ◽  
Hyun-Ung Oh

Abstract To overcome the theoretical limitations of Steinberg's theory for evaluating the mechanical safety of the solder joints of spaceborne electronics in a launch random vibration environment, a critical strain-based methodology was proposed and validated in a previous study. However, for the critical strain-based methodology to be used reliably in the mechanical design of spaceborne electronics, its effectiveness must be validated under various conditions of the package mounting locations and the first eigenfrequencies of a printed circuit board (PCB); achieving this validation is the primary objective of this study. For the experimental validation, PCB specimens with ball grid array packages mounted on various board locations were fabricated and exposed to a random vibration environment to assess the fatigue life of the solder joint. The effectiveness of the critical strain-based methodology was validated through a comparison of the fatigue life of the tested packages and their margin of safety, which was estimated using various analytical approaches.


2013 ◽  
Vol 706-708 ◽  
pp. 1693-1696
Author(s):  
Hua Bin Zhao ◽  
De Jian Zhou

In the study of three-dimensional shape prediction of SMT solder joints, the software Surface Evolver has been widely applied as a quick and accurate effective tool for the prediction of solder joints shape. But the model it builds is not able to be directly imported into any finite element analysis software like ANSYS, and even after the import it still needs a lot of time to mend the import model. For this issue, to predict of the solder joints shape of ball grid array (BGA), the implement programs of three conversion methods of point-line-area method, axisymmetric method and infinitesimal method are given. By comparison, axisymmetric method and infinitesimal method are more suitable for the shape conversion of BGA solder joints.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000534-000542
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
R. Ghaffarian

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of IC packages with conventional (small) stand-off heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: 1) attributes of the manufacturing process, 2) solder material properties and 3)design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the PCB-package assembly and particularly to the differences in the thermally induced curvatures of the PCB and the package. In this analysis the stress-and-warpage issue is addressed using an analytical predictive stress model. This model is a modification and an extension of the model developed back in 1980-s by the first author. It is assumed that it is the difference in the post-fabrication deflections of the PCB-package assembly that is the root cause of the solder materials failures and particularly and perhaps the HnP defects. The calculated data based on the developed analytical thermal stress model suggest that the replacement of the conventional ball-grid-array (BGA) designs with designs characterized by elevated stand-off heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design referred to as ball-grid-array (BGA) and a design with solder joints with elevated stand-off heights referred to as column-grid-array (CGA) are compared. The computed data indicated that the effective stress in the solder material is relieved by about 40% and the difference between the maximum deflections of the PCB and the package is reduced by about 60%, when the BGA design is replaced by a CGA system. Although no proof that the use of solder joints with elevated stand-off heights will lessen the package propensity to the HnP defects is provided, the authors think that there is a reason to believe that the application of solder joints with elevated stand-off heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.


2019 ◽  
Vol 38 ◽  
pp. 1138-1142
Author(s):  
Abid-Alrahman Fawzi Abbas ◽  
Christopher M. Greene ◽  
Krishnaswami Srihari ◽  
Daryl Santos ◽  
Ganesh Pandiarajan

2005 ◽  
Vol 127 (4) ◽  
pp. 466-473 ◽  
Author(s):  
B. L. Chen ◽  
X. Q. Shi ◽  
G. Y. Li ◽  
K. H. Ang ◽  
Jason P. Pickering

In this study, a thermoelectric cooler-based rapid temperature cycling (RTC) testing method was established and applied to assess the long term reliability of solder joints in tape ball grid array (TBGA) assembly. This RTC testing methodology can significantly reduce the time required to determine the reliability of electronic packaging components. A three-parameter Weibull analysis characterized with a parameter of failure free time was used for assembly reliability assessment. It was found that the RTC not only speedily assesses the long-term reliability of solder joints within days, but also has the similar failure location and failure mode observed in accelerated temperature cycling (ATC) test. Based on the RTC and ATC reliability experiments and the modified Coffin-Manson equation, the solder joint fatigue predictive life can be obtained. The simulation results were found to be in good agreement with the test results from the RTC. As a result, a new reliability assessment methodology was established as an alternative to ATC for the evaluation of long-term reliability of electronic packages.


2014 ◽  
Vol 936 ◽  
pp. 628-632 ◽  
Author(s):  
Guo Zheng Yuan ◽  
Xia Chen ◽  
Xue Feng Shu

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.


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