Structures and Materials of System in Package: A Review

2020 ◽  
Vol 13 ◽  
Author(s):  
Wenchao Tian ◽  
Chuqiao Wang ◽  
Zhanghan Zhao ◽  
Hao Cui
Keyword(s):  
System Integration ◽  
Semiconductor Industry ◽  
Academic Research ◽  
Packaging Materials ◽  
Technology System ◽  
Existing Problems ◽  
Technology Roadmap ◽  
Advanced Packaging ◽  
Thermomechanical Reliability ◽  
Packaging Structure

Background: As a new type of advanced packaging and system integration technology, System-in-Package (SiP) can realize the miniaturization and multi-functionalization of electronic products and is listed as an important direction of development by International Technology Roadmap for Semiconductors (ITRS). <P> Objective: This paper mainly introduces and discusses recent academic research and patents on package structure and packaging materials. Additionally, the trending of development is described. <P> Methods: Firstly, we analyze and summarize the challenges and existing problems in SiP. Then the corresponding solutions are introduced with respect to packaging structure and packaging materials. Finally, the research status of SIP and some patents in these aspects is reviewed. <P> Results: In order to increase the density of internal components, SiP products need to use a stacked structure. The cause of different performance in SiP products are: 1) the stress concentration and bonding quality problems caused by the chip stack structure; 2) the warpage and package thickness problems caused by the package stack; 3) Thermal conductivity of materials and thermal mismatch between materials; 4) Dielectric properties and thermomechanical reliability of materials. The following solutions are summarized: 1) Structural optimization of chip stacking and packaging stacking; 2) Application of new packaging technology; 3) Optimization of packaging materials; 4) Improvement of packaging material processing technology. <P> Conclusion: With the study of packaging structure and packaging materials, SiP can meet the requirements of the semiconductor industry and have great future prospects

scholarly journals A Fuzzy-MOP-Based Competence Set Expansion Method for Technology Roadmap Definitions

Mathematics ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 135
Author(s):  
Chi-Yo Huang ◽  
Jih-Jeng Huang ◽  
You-Ning Chang ◽  
Yen-Chu Lin
Keyword(s):  
Academic Research ◽  
Expansion Method ◽  
Management Tool ◽  
Research Database ◽  
Policy Makers ◽  
Technology Roadmapping ◽  
Technology Roadmap ◽  
High Technology Firms ◽  
Mathematical Programming Method ◽  
Intellectual Properties

Technology roadmaps have been widely adopted as an important management tool during the past three decades after their invention by Motorola in the 1980s. Technology roadmapping processes can be integrated with a firm’s competence sets and play dominant roles in strategy definitions. Although the issue of how multiple objectives can be dealt with in technology roadmaps by including the uncertainties of the modern management environment is important, it has seldom been addressed. To remedy this, we aim in this research to propose a competence set expansion method based on fuzzy multiple objective programming (FMOP). An empirical study based on the roadmapping of silicon intellectual properties (SIPs) of automotive applications will be used to demonstrate the feasibility of the proposed roadmapping method. In the future, the proposed analytic technique can be integrated with the data mining results of academic research database, patent libraries, etc. The well-verified mathematical programming method can serve as a basis for research and development (R&D) strategy definitions by managers of high-technology firms as well as policy makers of governments.

The Comparative Analysis of Cushion or Shock Absorption Characteristic of Commonly-Used Cushion Packaging Materials

2012 ◽  
Vol 490-495 ◽  
pp. 3902-3906 ◽  
Author(s):  
Zhen Jie Du ◽  
Wan Yu Gao ◽  
Hai Hong Kang ◽  
Sheng Jun Liu ◽  
Ming Xi Hu ◽  
...  
Keyword(s):  
Dynamic Compression ◽  
Static Stress ◽  
Final Conclusion ◽  
Absorption Characteristic ◽  
Packaging Materials ◽  
Shock Absorption ◽  
Static Test ◽  
Reference Information ◽  
Stress Curve ◽  
Packaging Structure

The purpose and method of this paper is to comparatively analyze several commonly-used cushion packaging materials, obtain their shock absorption characteristic curves, and by doing such, provide reference information for cushion packaging design and research. With the static test, dynamic compression test and vibration transfer test carried out, the cushion coefficient ~ static stress curve, maximal acceleration ~ static stress curve and vibration transfer rate ~ frequency curve are gained. A final conclusion is educed that in practical design routine, rational choice of cushion packaging materials, scientific design of packaging structure and validation of anti-vibration capability are relative to those three curves.

Advances in Fine Pitch Off-Chip Interconnections Through the Use of a Novel Surface Finish

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001531-001563
Author(s):  
Arnd Kilian ◽  
Gustavo Ramos ◽  
Rick Nichols ◽  
Robin Taylor ◽  
Vanessa Smet ◽  
...  
Keyword(s):  
Low Temperature ◽  
Surface Finish ◽  
System Integration ◽  
High Performance ◽  
Semiconductor Industry ◽  
Electroless Nickel ◽  
Interfacial Stress ◽  
Copper Oxidation ◽  
Fine Pitch ◽  
Metallurgical Bond

One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable. Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders. All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology. This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability. This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints. The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference. A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

The Growth of Advanced Packaging: An Overview of the Latest Technology Developments, Applications and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000001-000005 ◽  
Author(s):  
R. Beica ◽  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
J. Azemar
Keyword(s):  
Semiconductor Industry ◽  
Cost Effective ◽  
Cmos Technology ◽  
Advanced Technology ◽  
Current Trends ◽  
Advanced Packaging ◽  
Scaling Process ◽  
Market Trends ◽  
The Cost ◽  
Technology Nodes

The semiconductor industry, for more than five decades, has followed Moore's law and was driven by miniaturization of the transistors, scaling the CMOS technology to smaller and more advanced technology nodes while, at the same time, reducing the cost. The industry is reaching now limitations in continuing this scaling process in cost effective way. While technology nodes continue to be developed and innovative solutions are being proposed, the investment required to bring such technologies to production are significantly increasing. To overcome these limitations, new packaging technologies have been developed, enabling integration of more performing as well as various type of devices within the same package. This paper will provide an overview of current trends seen in the industry across all the packaging platforms (WLCSP1, FanOut2, Embedded Die2, Flip Chip3 and 3DIC4). Challenges, applications, positioning of the different packaging technologies by market segments (from low end to high end applications) and changes of the markets and drivers, growth rates and roadmaps will be presented. Global capacities and demands and the landscape of the packaging industry will be reviewed. Examples of teardowns to illustrate the latest packaging techniques for various devices used in latest products will be included.

Business Process Reengineering in the Automotive Area by Simulator-Based Design

2008 ◽  
pp. 337-358 ◽  
Author(s):  
Torbjörn Alm ◽  
Jens Alfredson ◽  
Kjell Ohlsson
Keyword(s):  
System Integration ◽  
New Technology ◽  
Process Reengineering ◽  
Mechatronic Systems ◽  
Good Correspondence ◽  
Design Work ◽  
Technology System ◽  
Institutional Goals ◽  
Human In The Loop ◽  
Computer Based

The automotive industry is facing economic and technical challenges. The economic situation calls for more efficient processes, not only production processes but also renewals in the development process. Accelerating design work and simultaneously securing safe process outcome leads to products in good correspondence with market demands and institutional goals on safe traffic environments. The technique challenge is going from almost pure mechanical constructions to mechatronic systems, where computer-based solutions may affect core vehicle functionality. Since subcontractors often develop this new technology, system integration is increasingly important for the car manufacturers. To meet these challenges we suggest the simulator-based design approach. This chapter focuses on human-in-the- loop simulation, which ought to be used for design and integration of all car functionality affecting the driver. This approach has been proved successful by the aerospace industry, which in the late 1960s recognized a corresponding technology shift.

Reliability and Lifing Methodologies for Microelectronic Systems

1998 ◽  
Vol 515 ◽  
Author(s):  
Ken Reifsnider
Keyword(s):  
Semiconductor Industry ◽  
Turn Of The Century ◽  
Operating Conditions ◽  
Interactive Effects ◽  
Design Development ◽  
Component Level ◽  
Composite Systems ◽  
Technology Roadmap ◽  
Mechanical Models ◽  
Chemical Conditions

ABSTRACTIntegration of core electronic functions is progressing at a remarkable rate. The high-end computers that we are using now may be available on a single die by the turn of the century. The effect of this, and other advances on semiconductor assembly and packaging has generated the need for integrated component-level electrical thermal, and mechanical models and simulation methods, as described in the Semiconductor Industry Association national Technology Roadmap for Semiconductors. Although corporate and university research and development in the semiconductor area is intense (there are eight major university-based packaging centers around the world, for example), design/development methodologies that consider the combined and interactive effects of mechanical, thermal and chemical conditions on the reliability and durability of integrated components have been slow to develop. However, such methodologies have been developed for applications of complex composite systems in various other technologies where the operating conditions are similar. The present paper will discuss those developments and the possibility of applying that technology to microelectronic systems.

scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

The Theory of Green Packaging Design and its Application

2014 ◽  
Vol 635-637 ◽  
pp. 248-252 ◽  
Author(s):  
Fen Fen Zhou
Keyword(s):  
Structure Design ◽  
Living Environment ◽  
Packaging Materials ◽  
Human Society ◽  
Design Work ◽  
Packaging Design ◽  
Green Packaging ◽  
The Times ◽  
The One ◽  
Packaging Structure

With the development of science and technology and the progress of human society,We gradually know that survival environment is worsening,the further development of the economy has been restricted.These problems directly affect the reproduction of human civilization,So our country put forward the strategy of sustainable development.The concept of green packaging design is adapted to the demand of the times,in order to explore the application of the green idea in the packaging design.Green packaging design needs to consider packaging materials,this will affect the packaging cost.The 60% ~ 80% of the packaging cost have been confirmed in the product design stage.Green packaging structure design should be considered,the structure of reasonable design of packaging, not only can reduce cost, but also reduce the adverse impact on the environment.When we need to use the least amount of packaging materials,a sphere is the best choice.The height of the cylinder is equal to the radius of 2 times through calculation,Its surface area is smallest.Green packaging, therefore, on the one hand, can avoid the waste of resources,let our design work can be harmonious with our living environment.

Sign in / Sign up

Export Citation Format

Share Document