A High-Performance Mel-scale Frequency Cepstral Coefficients Digital Circuit Used on Keyword-Spotting Chip

2021 ◽  
Author(s):  
Jiankun Huang ◽  
Xinjie Feng ◽  
Congying Zhou ◽  
Yongzhen Chen
Keyword(s):  
High Performance ◽  
Digital Circuit ◽  
Keyword Spotting ◽  
Cepstral Coefficients

scholarly journals Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 482
Author(s):  
Mangi Han ◽  
Youngmin Kim
Keyword(s):  
High Performance ◽  
Electronic Device ◽  
Finite Impulse Response ◽  
Parallel Implementation ◽  
Power Level ◽  
Digital Signal ◽  
Digital Circuit ◽  
Output Power Level ◽  
Verilog Hdl ◽  
Field Programmable

In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

scholarly journals Energy Efficient SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1086-1091
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Static Noise Margin ◽  
Noise Margin ◽  
And Performance ◽  
The Stability ◽  
Static Noise

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

scholarly journals Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

2019 ◽  
Vol 8 (9) ◽  
pp. 2007-2014
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Arithmetic Operation ◽  
Digital Signal ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Digital Circuit Design ◽  
Unit Design ◽  
High Performance Systems ◽  
Signal Processors

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals Fuzzy Processing Implementation in Dedicated Digital Hardware

2010 ◽  
Vol 56 (4) ◽  
pp. 405-410 ◽  
Author(s):  
Przemysław Szecówka ◽  
Adam Musiał
Keyword(s):  
Fuzzy Sets ◽  
High Performance ◽  
Digital Circuit ◽  
Synchronous Machine ◽  
Floating Point ◽  
Weighted Sum ◽  
Sample Design ◽  
Floating Point Arithmetic ◽  
Digital Hardware ◽  
Point Arithmetic

Fuzzy Processing Implementation in Dedicated Digital HardwareThe paper presents a concept of digital circuit dedicated for fuzzy processing with numerical inputs and outputs. Partially concurrent and pipelined data flow provides high performance, with relatively low dependence on particular algorithm complexity. Sample design with triangular fuzzy sets, rule strength calculation (minimumapproach) and defuzzyfication by weighted sum of fuzzy sets centers was implemented in VHDL, verified and synthesized for FPGA. Floating point arithmetic was applied, including dvision performed by dedicated synchronous machine. All modules were prepared for easy reuse/redesign.

scholarly journals Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

2014 ◽  
Vol 12 (8) ◽  
pp. 3803-3808 ◽  
Author(s):  
Shilpa Kamde ◽  
Jitesh Shinde ◽  
Sanjay Badjate ◽  
Pratik Hajare
Keyword(s):  
High Speed ◽  
High Performance ◽  
Circuit Simulation ◽  
Dynamic Logic ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Vlsi Circuit ◽  
Short Channel ◽  
Domino Logic ◽  
Low Area

Domino logic is a CMOS-based evolution of the dynamic logic  techniques  based  on  either  PMOS  or  NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

scholarly journals Optimization of CNFET Parameters for High Performance Digital Circuits

2016 ◽  
Vol 2016 ◽  
pp. 1-9 ◽  
Author(s):  
Shimaa Ibrahim Sayed ◽  
Mostafa Mamdouh Abutaleb ◽  
Zaki Bassuoni Nossair
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Operating Voltage ◽  
Circuit Performance ◽  
Contact Materials ◽  
Strong Candidate ◽  
Power Delay Product ◽  
Near Future

The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.

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