Validating circuit board Interconnect Stress Test preconditioning processes using statistical model comparisons of accelerated test data

2009 ◽  
Vol 25 (7) ◽  
pp. 885-895
Author(s):  
Joseph M. Juarez ◽  
Vicka White
Keyword(s):  
Statistical Model ◽  
Test Data ◽  
Stress Test ◽  
Circuit Board ◽  
Accelerated Test ◽  
Model Comparisons

A Processing Method for Combined Fatigue Accelerated Test Data

2017 ◽  
Author(s):  
Songwang Zheng ◽  
Cao Chen ◽  
Lei Han ◽  
Xiaoyong Zhang ◽  
Xiaojun Yan
Keyword(s):  
Data Processing ◽  
Test Data ◽  
Turbine Blades ◽  
Processing Method ◽  
Test Time ◽  
Accelerated Test ◽  
The Real ◽  
Data Processing Method ◽  
Stress Levels ◽  
Vibration Stress

To carry out combined low and high cycle fatigue (CCF) test on turbine blades in a bench environment, it is imperative to simulate the vibration loads of turbine blades in the field. Due to the low vibration stress of turbine blades in the working state, the test time will be very long if the test vibration stress is equal to the real vibration stress in working state. Therefore, an accelerated test will be used when the test life reach the target value (typically 107). During the accelerated test, each blade is tested at two or more times than the real vibration stress. That means some specimens are tested under two vibration stress levels. In this case, a reasonable data processing method becomes very important. For this reason, a data processing method for the CCF accelerated test is proposed in this paper. These test data are iterated on the basis of S-N curve. Finally, ten real turbine blades are tested in a bench environment, one of them is tested under two vibration stress levels. The test data is processed using the method proposed above to obtain the unaccelerated life data.

Electromigration in Power Devices

2020 ◽  
Vol 2020 (1) ◽  
pp. 000078-000084
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Circuit Board ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Printed Circuit Board Pad Crater Test Methods and Sample Design

2012 ◽  
Author(s):  
Todd Embree ◽  
Deassy Novita ◽  
Gary Long ◽  
Satish Parupalli
Keyword(s):  
Test Data ◽  
Printed Circuit Board ◽  
Test Methods ◽  
Circuit Board ◽  
Lead Free ◽  
Sample Design ◽  
Printed Circuit ◽  
Highly Sensitive ◽  
Halogen Free ◽  
Lead Free Solders

The continual drive toward smaller second level interconnect dimensions, along with the introduction of Halogen-Free circuit board materials and increased process temperatures of Lead-Free solders, have all contributed to a more frequent occurrence of Pad Crater damage in circuit board materials during manufacturing and test processes. This paper addresses the methodology and test data of some common industry methods used to evaluate Pad Crater strength in circuit board materials. Pad Crater test data is highly sensitive to sample design; as a result a discussion of sample design criteria is also included.

PCR for Derivation of Parameter Dependencies, Thermo-Mechanical Norris-Landzberg Acceleration Factors, Goldmann Fatigue Constants for Leadfree Electronics

2009 ◽  
Author(s):  
Pradeep Lall ◽  
Aniket Shirgaokar ◽  
Dineshkumar Arunachalam ◽  
Jeff Suhling ◽  
Mark Strickland ◽  
...  
Keyword(s):  
Test Data ◽  
Thermal Cycle ◽  
Regression Models ◽  
Reliability Prediction ◽  
Maximum Temperature ◽  
Temperature Cycle ◽  
Data Sets ◽  
Accelerated Test ◽  
Bga Packages ◽  
Part Selection

Goldmann Constants and Norris-Landzberg acceleration factors for lead-free solders have been developed based on principal component regression models (PCR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Models have been developed in conjunction with Stepwise Regression Methods for identification of the main effects. Package architectures studied include, BGA packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermo-mechanical failure data. Data has been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Goldmann Constants and the Norris-Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation data-sets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experiment study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages [Lall 2004, 2005], flip-chip packages [Lall 2005] and ceramic BGA packages [Lall 2007]. The presented methodology is valuable in the development of fatigue damage constants for the application specific accelerated test data-sets and provides a method to develop institutional learning based on prior accelerated test data.

In-Situ Stress Test Data - Revelation to Optimisation of Stimulation Strategy of an Unconventional Reservoir

2013 ◽  
Author(s):  
Mohit Mathur ◽  
Aditya Ojha ◽  
Sourabh Shukla ◽  
Anish Gupta ◽  
Manabesh Chowdhury
Keyword(s):  
Test Data ◽  
Stress Test ◽  
In Situ Stress ◽  
Unconventional Reservoir

Damage and Failures of CGA/BGA Assemblies Under Thermal Cycling and Dynamic Loadings

2013 ◽  
Author(s):  
Reza Ghaffarian
Keyword(s):  
Thermal Cycling ◽  
Mechanical Loading ◽  
Test Data ◽  
Printed Circuit Board ◽  
High Reliability ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Space Applications ◽  
High Processing

Commercial-off-the-shelf column/ball grid array packaging (COTS CGA/BGA) technologies in high-reliability versions are now being considered for use in high-reliability electronic systems. For space applications, these packages are prone to early failure due to the severe thermal cycling in ground testing and during flight, mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of solder interconnections decreases, susceptibility to thermal, mechanical loading and cycling fatigue grows even more. This paper reviews technology as well as thermo-mechanical reliability of field programmable gate array (FPGA) IC packaging developed to meet demands of high processing powers. The FPGAs that generally come in CGA/PBGA packages now have more than thousands of solder balls/columns under the package area. These packages need not only to be correctly joined onto printed circuit board (PCB) for interfacing; they also should show adequate system reliability for meeting thermo-mechanical requirements of the electronics hardware application. Such reliability test data are rare or none for harsher environmental applications, especially for CGAs having more than a thousand of columns. The paper also presents significant test data gathered under thermal cycling and drop testing for high I/O PBGA/CGA packages assembled onto PCBs. Damage and failures of these assemblies after environmental exposures are presented in detail. Understanding the key design parameters and failure mechanisms under thermal and mechanical conditions is critical to developing an approach that will minimize future failures and will enable low-risk insertion of these advanced electronic packages with high processing power and in-field re-programming capability.

Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection

2019 ◽  
Vol 2019 (1) ◽  
pp. 000216-000222
Author(s):  
Chun-Hsien Chien ◽  
Chien-Chou Chen ◽  
Wen-Liang Yeh ◽  
Wei-Ti Lin ◽  
Cheng-Hui Wu ◽  
...  
Keyword(s):  
Stress Test ◽  
Dielectric Materials ◽  
Circuit Board ◽  
Strip Line ◽  
Organic Substrates ◽  
Next Generation ◽  
Glass Panel ◽  
Process Technology ◽  
Fine Line ◽  
Ic Foundry

Abstract In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.

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