scholarly journals The Proof of Correctness of a Fault-Tolerant Circuit Design

1992 ◽  
pp. 243-260 ◽  
Author(s):  
William R. Bevier ◽  
William D. Young
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Proof Of Correctness

3A Fault Tolerant Low Side Driver Circuit Design Using Design FMEA for Automotive Applications

2019 ◽  
Author(s):  
Sri Navaneeth Easwaran ◽  
Martin Mollat ◽  
Deepak Sreedharan ◽  
Samir Camdzic ◽  
Sunil Venugopal Kashvap ◽  
...  
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Automotive Applications ◽  
Driver Circuit

scholarly journals SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

2014 ◽  
Vol 54 (4) ◽  
pp. 738-745 ◽  
Author(s):  
A. Calomarde ◽  
E. Amat ◽  
F. Moll ◽  
J. Vigara ◽  
A. Rubio
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Design Techniques

Evolving Fault Tolerant System Based on FPGA

2013 ◽  
Vol 341-342 ◽  
pp. 819-823
Author(s):  
Jia Nan Lou ◽  
Yang Li
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Design Method ◽  
High Reliability ◽  
Dynamically Reconfigurable ◽  
Dc Motor Control ◽  
Motor Control System ◽  
Adaptive Circuit ◽  
Circuit Function ◽  
Control Part

In order to overcome the single event function interrupt and SA failure, this paper proposes and implements a new way to design circuit, i.e. dynamically reconfigurable adaptive circuit design method. We load a Microblaze which is a soft CPU in FPGA as a motion control part of the circuit, as well as use some place of FPGA as evolution pool to find target circuit. Microblaze known input and the corresponding output applies genetic algorithm to search evolution pool. Depend on it, we successfully design and implement a DC Motor control system, besides, we carry out theoretical analysis on this circuit reliability and simulate circuit function repair test of SA fault, the result demonstrates that compared with the traditional circuit, this circuit and has a high reliability.

scholarly journals Low Leakage Approximate multiplier design for high Performance Error Tolerant Applications

2021 ◽  
Vol 58 (2) ◽  
pp. 5657-5661
Author(s):  
Supratim Saha, Dr. Amit Kumar Jain
Keyword(s):  
Circuit Design ◽  
Calculation Method ◽  
Power Dissipation ◽  
High Performance ◽  
Fault Tolerant ◽  
Leakage Power ◽  
Vlsi Circuit ◽  
Control Techniques ◽  
Low Leakage ◽  
Performance Error

Power dissipation has become a major concern in VLSI circuit design with the rapid launch of battery powered applications. In high-performance constructions, the leakage component of power consumption is comparable to the switching component. This percentage increases as the technology scales unless effective leak control techniques are in place. In the case of fault-tolerant applications it is also not necessary to adhere to the exact calculation method. Therefore, an approximate multiplier of 8 x 8 is developed in this article using several proposed techniques to reduce leakage power such as MTCMOS, DUAL-Vt, and LECTOR. All of the above techniques are simulated with a tanning tool using 90 nm technology.

scholarly journals A Fault-tolerant Sequential Circuit Design for Stuck-at Faults and Path Delay Faults

2017 ◽  
pp. 61-68
Author(s):  
Anjela Yurievna Matrosova ◽  
◽  
Sergey Alexandrovich Ostanin ◽  
Irina Evgenievna Kirienko ◽  
Ekaterina Alexandrovna Nikolaeva
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Delay Faults ◽  
Path Delay ◽  
Path Delay Faults ◽  
Sequential Circuit

A fault-tolerant combinational circuit design

2015 ◽  
Author(s):  
S. Ostanin ◽  
I. Kirienko ◽  
V. Lavrov
Keyword(s):  
Circuit Design ◽  
Fault Tolerant ◽  
Combinational Circuit

scholarly journals Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design

2007 ◽  
Author(s):  
Huifei Rao ◽  
Jie Chen ◽  
Changhong Yu ◽  
Woon Tiong Ang ◽  
I-Chyn Wey ◽  
...  
Keyword(s):  
Circuit Design ◽  
Fault Tolerant

A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage

2018 ◽  
Vol 6 (8) ◽  
pp. 235
Author(s):  
S. Ravichand ◽  
T. Madhu ◽  
M. Sailaja
Keyword(s):  
Genetic Algorithm ◽  
Circuit Design ◽  
Fault Tolerant ◽  
Current System ◽  
Satellite Broadcasting ◽  
Area Overhead ◽  
Free Block ◽  
Utmost Care ◽  
Logical Errors ◽  
Active Block

In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit.  This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.

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