Synergetic effects of wafer rigidity and retaining-ring parameters on contact stress uniformity in chemical mechanical planarization

Here we use 2-D models of fluid film lubrication and contact mechanics to calculate the contact stress and fluid (i.e., slurry) pressure distributions on the wafer–pad interface in CMP. In particular, the effective rigidity of the wafer (determined by the wafer carrier structure), the retaining ring width and its back pressure are taken to be the design parameters. The purpose is to study the synergetic effects of such parameters on the contact stress non-uniformity (NU), which directly affects the spatial non-uniformity of the material removal rate on the wafer surface. Our numerical results indicate that, for a given wafer rigidity, one may choose a particular combination of the retaining ring parameters to minimize NU. Also, the corresponding minimum NU decreases with the effective wafer rigidity, suggesting that it is beneficial to use a soft (e.g., floating-type) wafer carrier. Moreover, for a soft wafer carrier, the presence of the retaining ring also reduces NU to some extent, but the use of a multi-zone wafer-back pressure profile would be more effective in this regard.

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Improvement of Wafer Edge Profile and Cmp Performance Through The Floating Head Design

MRS Proceedings ◽

10.1557/proc-613-e5.1.1 ◽

2000 ◽

Vol 613 ◽

Author(s):

Huey-Ming Wang ◽

Gerry Moloney ◽

Mario Stella ◽

Sesinando Deguzman

Keyword(s):

Chemical Mechanical Planarization ◽

Pressure Chamber ◽

Point Of View ◽

Thickness Variation ◽

Deformation Control ◽

Edge Profile ◽

Retaining Ring ◽

Floating Type ◽

Edge Exclusion ◽

Wafer Edge

ABSTRACTThe dependence of IC fabrication on the Chemical Mechanical Planarization (CMP) process increases as the device features go down to 0.25 micron or beyond. Due to the tighter CMP process spec, it is very important to reduce the within wafer non-uniformity (WIWNU%) to achieve higher process yield. The symmetrical increment of linear velocity at wafer edge is not sufficient to change wafer edge profile by breaking the matched speed rule. A better solution is through the change of head design for a fixed platen from the polisher design point of view. This study demonstrates the improvement of the CMP process performance, especially at the wafer edge, from the modification of the floating type polish head. The best WIWNU% from a single air chamber head is about 5.12% at 6-mm edge exclusion (EE). In order to obtain better pad deformation control, the retaining-ring pressure chamber is separated from that of the sub-carrier. The average WIWNU% is about 4% for 3-mm and 5-mm EE from two-pressure-chamber head. Due to the limitation of retaining-ring pressure effect, a third pressure chamber is further added that can be extended the edge control up to 1 inch from the wafer edge. The WIWNU% is about 3.8% at 5-mm edge exclusion with low down forces. The slurry and insert types also show effect on the wafer edge profile. It has been also proven that this three-pressure-chamber head is able to reduce the post-CMP thickness variation from the ILD production wafer, especially at wafer edges. More detailed information and CMP mechanism will be discussed in this paper.

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Effect of Retaining Ring Slot Designs, Conditioning Discs and Conditioning Schemes on the Slurry Bow Wave Width during Chemical Mechanical Planarization

ECS Journal of Solid State Science and Technology ◽

10.1149/2.0141805jss ◽

2018 ◽

Vol 7 (5) ◽

pp. P253-P259 ◽

Cited By ~ 5

Author(s):

Leticia Vazquez Bengochea ◽

Yasa Sampurno ◽

Calliandra Stuffle ◽

Fransisca Sudargho ◽

Ruochen Han ◽

...

Keyword(s):

Chemical Mechanical Planarization ◽

Bow Wave ◽

Retaining Ring

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Contact stress analysis of disc cutter peg-hole with interference fit

Transactions of the Canadian Society for Mechanical Engineering ◽

10.1139/tcsme-2018-0130 ◽

2019 ◽

Vol 43 (3) ◽

pp. 273-282

Author(s):

Jie Li ◽

Chao Ma ◽

Bin Zhang ◽

Yuanjun Huang ◽

Jingbo Guo

Keyword(s):

Thermal Expansion ◽

Contact Stress ◽

Contact Length ◽

Radial Force ◽

Disc Cutter ◽

The Finite Element Method ◽

Interference Fit ◽

Mating Surface ◽

Retaining Ring ◽

Surface Increase

To study the relation of the interference fit between cutter body and cutter ring, a theoretical design of interference fit of the cutter peg-hole is carried out according to the theory of thick-walled cylinders. The finite element method is used to analyzed the mapping relationship between the contact stress of cutter ring and cutter body. Thermal expansion assembly of the cutter ring is simulated, and the temperature of the thermal expansion assembly of the cutter ring is determined. The result shows that the contact length between the cutter body and the cutter ring has little influence on the contact stress of the cutter ring, but with increasing contact length the stress concentration of the retaining ring will increase. The contact stress of the cutter ring is basically the same at the same amount of interference and temperature, but the contact stress of the ring decreases with increasing contact length at high temperature. When the contact length is the same, the contact stress and the radial force of the mating surface increase with increasing amount of interference. The reasonable temperature for thermal expansion assembly of the cutter ring is 160 °C.

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Retaining Ring Design Impact on CMP Process Stability and Optimization

MRS Proceedings ◽

10.1557/proc-1249-e02-01 ◽

2010 ◽

Vol 1249 ◽

Cited By ~ 3

Author(s):

Joseph Smith ◽

Christopher Wargo ◽

Raghava Kakireddy ◽

Rakesh Singh ◽

Andrew Galpin ◽

...

Keyword(s):

Removal Rate ◽

Chemical Mechanical Planarization ◽

High Volume ◽

Major Effect ◽

Process Conditions ◽

Process Stability ◽

Wafer Level ◽

Lubrication Regimes ◽

Retaining Ring ◽

Wafer Processing

AbstractThe focus of this work is wafer retaining rings and their impact on chemical mechanical planarization (CMP) process stability, yield, and overall cost of ownership (CoO). The study looks at various CMP retaining ring materials and processing methods. Tribological investigations as well as wafer processing are critical to understand the retaining ring and polishing pad environment. Interactions at the ring/pad interface have a major effect on the planarization and defectivity of a polished wafer. Shear and normal forces at this interface, as well as temperature and lubrication regimes, were monitored to establish an empirical model. All process conditions equal, the material properties of retaining rings govern the coefficient of friction (COF) in the ring and pad contact area. Present study demonstrates a lower COF to be an indicator of extended ring lifetime, decreasing WTWNU and removal rate (RR) variation. The study correlates the findings on wafer level data from high volume manufacturing fabs with empirical data generated using applications lab tribological equipment to understand the on-wafer performance as a function of retaining ring material. The study's further aim is to understand for specific applications, the material interactions on-wafer using various retaining ring materials. CMP process optimization can be attained with a better understanding of retaining ring design and material characteristics, as well as polishing head and slurry parameters.

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Chemical-Mechanical Planarization of Semiconductor Materials

10.1007/978-3-662-06234-0 ◽

2004 ◽

Cited By ~ 85

Keyword(s):

Chemical Mechanical Planarization ◽

Semiconductor Materials

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A Latent Issue of Via Resistance: Mechanism and Solution

10.31399/asm.cp.istfa2018p0121 ◽

2018 ◽

Author(s):

Wentao Qin ◽

Scott Donaldson ◽

Dan Rogers ◽

Lahcen Boukhanfra ◽

Julien Thiefain ◽

...

Keyword(s):

Thermal Stress ◽

Chemical Mechanical Planarization ◽

Resistance Mechanism ◽

Formation Enthalpy ◽

Metal Line ◽

Device Failure ◽

Valence Electrons ◽

Wafer Processing ◽

Field Failure ◽

And Tungsten

Abstract Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

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Improved Burn-In Stress Methodology for Stress Uniformity

10.31399/asm.cp.istfa2018p0477 ◽

2018 ◽

Author(s):

Jungsuk Ko ◽

Hoonchang yang ◽

Hyungchae Jeon ◽

Gyuyoung Nam ◽

Youngseok Ryu ◽

...

Keyword(s):

Temperature Stress ◽

Stress Condition ◽

Temperature Deviation ◽

Stress Effects ◽

Hot Temperature ◽

Production Environments ◽

Stress Environment ◽

The Stability ◽

Stress Uniformity ◽

Stress Voltage

Abstract The necessity of hot temperature stress is widely recognized as the initial stress methodology to maintain the stability of products from infant defects in device [1, 2]. However, hot temperature stress has a disadvantage in terms of stress uniformity because temperature variation according to stress environment such as chamber, board, and tester accelerates different stress effects per chips. In addition, this stress condition can cause serious reliability problem in the mass production environments. Therefore, the stress temperature should be lowered to minimize the temperature deviation due to the production environments. The reduction of stress temperature cause the lack of stress amount, so optimized stress voltage and time to maintain the stress condition is required. In this study, various stress voltage and time with decreasing temperature were evaluated in consideration of lifetime that unit elements such transistors and capacitors did not degrade by any stress conditions. In addition, it was confirmed that stress uniformity can be improved in the stress condition obtained by the evaluation. Furthermore, the enhanced initial failure screen ability was proven with mass evaluations.

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A Proof for the Possibility of Ce-Oxide from CMP Residuals in Si-Wafers by Analytical TEM

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0347 ◽

2012 ◽

Author(s):

Wayne Zhao ◽

Liem Do Thanh ◽

Michael Gribelyuk ◽

Mary-Ann Zaitz ◽

Wing Lai

Keyword(s):

Technology Development ◽

Early Stage ◽

Chemical Mechanical Planarization ◽

Particle Cluster ◽

Limited Region ◽

Physical Evidence ◽

Analytical Tem ◽

Transmission Electron ◽

Oxide Particles

Abstract Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.

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