Retaining Ring Design Impact on CMP Process Stability and Optimization

2010 ◽  
Vol 1249 ◽  
Author(s):  
Joseph Smith ◽  
Christopher Wargo ◽  
Raghava Kakireddy ◽  
Rakesh Singh ◽  
Andrew Galpin ◽  
...  
Keyword(s):  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
High Volume ◽  
Major Effect ◽  
Process Conditions ◽  
Process Stability ◽  
Wafer Level ◽  
Lubrication Regimes ◽  
Retaining Ring ◽  
Wafer Processing

AbstractThe focus of this work is wafer retaining rings and their impact on chemical mechanical planarization (CMP) process stability, yield, and overall cost of ownership (CoO). The study looks at various CMP retaining ring materials and processing methods. Tribological investigations as well as wafer processing are critical to understand the retaining ring and polishing pad environment. Interactions at the ring/pad interface have a major effect on the planarization and defectivity of a polished wafer. Shear and normal forces at this interface, as well as temperature and lubrication regimes, were monitored to establish an empirical model. All process conditions equal, the material properties of retaining rings govern the coefficient of friction (COF) in the ring and pad contact area. Present study demonstrates a lower COF to be an indicator of extended ring lifetime, decreasing WTWNU and removal rate (RR) variation. The study correlates the findings on wafer level data from high volume manufacturing fabs with empirical data generated using applications lab tribological equipment to understand the on-wafer performance as a function of retaining ring material. The study's further aim is to understand for specific applications, the material interactions on-wafer using various retaining ring materials. CMP process optimization can be attained with a better understanding of retaining ring design and material characteristics, as well as polishing head and slurry parameters.

Novel Slurry Injection System for Improved Slurry Flow and Reduced Defects in CMP

2014 ◽  
Vol 219 ◽  
pp. 143-147 ◽  
Author(s):  
Ara Philipossian ◽  
Len Borucki ◽  
Yasa Sampurno ◽  
Yun Zhuang
Keyword(s):  
Removal Rate ◽  
Pressure Control ◽  
Injection System ◽  
Residual Water ◽  
Reaction Products ◽  
Wafer Level ◽  
Slurry Flows ◽  
Retaining Ring ◽  
Slurry Injection

In commercial CMP tools, slurry is applied near the pad center. As the pad rotates, more than 95% of the fresh slurry flows directly off the surface due to bow wave formation and inertial forces without ever entering the pad-wafer interface, resulting in low slurry utilization [1]. Furthermore, some slurry that manages to go under the wafer stays on the pad, mixes with fresh slurry and re-enters the pad-wafer interface. This used slurry contains reaction products, foam and pad debris (due to pad conditioning) that cause wafer-level defects [2]. Such defect-causing by-products keep recirculating on the pad during polishing and accumulate near the retaining ring over time. Also, since large amounts of DI water are used between wafer polishes to rinse off the debris and reaction products, appreciable amounts of water may stay on the pad and inside the grooves. When fresh slurry is introduced to polish the next wafer, it mixes with the residual water and is diluted, resulting in lower material removal. As such, the current slurry application method does not provide efficient slurry utilization and leaves significant room for improving defect levels. Moreover, the constant sweeping of the conditioner arm during in-situ conditioning results in uneven slurry distribution and introduces additional challenges when it comes to carrier multi-zone pressure control for reduced within-wafer removal rate non-uniformity.

A Latent Issue of Via Resistance: Mechanism and Solution

2018 ◽  
Author(s):  
Wentao Qin ◽  
Scott Donaldson ◽  
Dan Rogers ◽  
Lahcen Boukhanfra ◽  
Julien Thiefain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Chemical Mechanical Planarization ◽  
Resistance Mechanism ◽  
Formation Enthalpy ◽  
Metal Line ◽  
Device Failure ◽  
Valence Electrons ◽  
Wafer Processing ◽  
Field Failure ◽  
And Tungsten

Abstract Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

scholarly journals Enhanced Wastewater Treatment by Immobilized Enzymes

2021 ◽  
Author(s):  
Jakub Zdarta ◽  
Katarzyna Jankowska ◽  
Karolina Bachosz ◽  
Oliwia Degórska ◽  
Karolina Kaźmierczak ◽  
...  
Keyword(s):  
Wastewater Treatment ◽  
Process Optimization ◽  
Organic Pollutants ◽  
Large Scale ◽  
Removal Rate ◽  
Immobilized Enzymes ◽  
Future Research ◽  
Process Conditions ◽  
Removal Rates ◽  
Catalytic Cycles

Abstract Purpose of Review In the presented review, we have summarized recent achievements on the use of immobilized oxidoreductases for biodegradation of hazardous organic pollutants including mainly dyes, pharmaceuticals, phenols, and bisphenols. In order to facilitate process optimization and achievement of high removal rates, effect of various process conditions on biodegradation has been highlighted and discussed. Recent Findings Current reports clearly show that immobilized oxidoreductases are capable of efficient conversion of organic pollutants, usually reaching over 90% of removal rate. Further, immobilized enzymes showed great recyclability potential, allowing their reuse in numerous of catalytic cycles. Summary Collected data clearly indicates immobilized oxidoreductases as an efficient biocatalytic tools for removal of hazardous phenolic compounds, making them a promising option for future water purification. Data shows, however, that both immobilization and biodegradation conditions affect conversion efficiency; therefore, process optimization is required to achieve high removal rates. Nevertheless, we have demonstrated future trends and highlighted several issues that have to be solved in the near-future research, to facilitate large-scale application of the immobilized oxidoreductases in wastewater treatment.

scholarly journals Novel Abrasive-Impregnated Pads and Diamond Plates for the Grinding and Lapping of Single-Crystal Silicon Carbide Wafers

2021 ◽  
Vol 11 (4) ◽  
pp. 1783
Author(s):  
Ming-Yi Tsai ◽  
Kun-Ying Li ◽  
Sun-Yu Ji
Keyword(s):  
Silicon Carbide ◽  
Wear Rate ◽  
Single Crystal ◽  
Traditional Method ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Diamond Grit ◽  
Ceramic Binder

In this study, special ceramic grinding plates impregnated with diamond grit and other abrasives, as well as self-made lapping plates, were used to prepare the surface of single-crystal silicon carbide (SiC) wafers. This novel approach enhanced the process and reduced the final chemical mechanical planarization (CMP) polishing time. Two different grinding plates with pads impregnated with mixed abrasives were prepared: one with self-modified diamond + SiC and a ceramic binder and one with self-modified diamond + SiO2 + Al2O3 + SiC and a ceramic binder. The surface properties and removal rate of the SiC substrate were investigated and a comparison with the traditional method was conducted. The experimental results showed that the material removal rate (MRR) was higher for the SiC substrate with the mixed abrasive lapping plate than for the traditional method. The grinding wear rate could be reduced by 31.6%. The surface roughness of the samples polished using the diamond-impregnated lapping plate was markedly better than that of the samples polished using the copper plate. However, while the surface finish was better and the grinding efficiency was high, the wear rate of the mixed abrasive-impregnated polishing plates was high. This was a clear indication that this novel method was effective and could be used for SiC grinding and lapping.

High-Throughput Picosecond Laser Machining of Aerospace Nickel Superalloy

2021 ◽  
pp. 095440542110288
Author(s):  
Sundar Marimuthu ◽  
Bethan Smith
Keyword(s):  
Surface Roughness ◽  
Material Removal Rate ◽  
Material Removal ◽  
Thermal Damage ◽  
Removal Rate ◽  
Picosecond Laser ◽  
Nickel Superalloy ◽  
Laser Machining ◽  
Process Conditions ◽  
Machining Performance

This manuscript discusses the experimental results on 300 W picosecond laser machining of aerospace-grade nickel superalloy. The effect of the laser’s energetic and beam scanning parameters on the machining performance has been studied in detail. The machining performance has been investigated in terms of surface roughness, sub-surface thermal damage, and material removal rate. At optimal process conditions, a picosecond laser with an average power output of 300 W can be used to achieve a material removal rate (MRR) of ∼140 mm3/min, with thermal damage less than 20 µm. Shorter laser pulse widths increase the material removal rate and reduce the resultant surface roughness. High scanning speeds improve the picosecond laser machining performance. Edge wall taper of ∼10° was observed over all the picosecond laser machined slots. The investigation demonstrates that high-power picosecond lasers can be used for the macro-machining of industrial components at an acceptable speed and quality.

Effects of Alkaline Nano-SiO2 Abrasive on Planarization of 300mm Copper Patterned Wafer

2013 ◽  
Vol 634-638 ◽  
pp. 2949-2954
Author(s):  
Xin Liang Tang ◽  
Yu Ling Liu ◽  
Hong Yuan Zhang ◽  
Jie Bao
Keyword(s):  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Initial Step ◽  
Step Height ◽  
Copper Removal ◽  
Copper Wafers

Silica abrasive plays an important role in chemical mechanical planarization (CMP) of copper. In this paper, effect of different silica abrasive concentrations on copper removal rate and planarization performance of copper was investigated. The results show that the copper removal rate was increased as the concentration of silica abrasive increase. However, excessive abrasive will lead to a decreased copper removal rate. The initial step height values of the multilayer copper wafers were all about 2500Å, and after being polished for 30s, the remaining values of step height of slurry A, B, C and D were 717 Å, 906 Å, 1222 Å and 1493 Å. It indicates that alkaline copper slurries with different abrasive concentrations all had a good planarization performance on copper patterned wafer CMP. As the abrasive concentration increased, the planarization capability was enhanced.

Effects of Additives in KOH Based Electrolytes on Cu ECMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Tae-Young Kwon ◽  
In-Kwon Kim ◽  
Jin-Goo Park
Keyword(s):  
Citric Acid ◽  
Applied Voltage ◽  
Counter Electrode ◽  
Corrosion Potential ◽  
Removal Rate ◽  
Chemical Mechanical Planarization ◽  
Corrosion Current ◽  
Dynamic State ◽  
Static State ◽  
Potentiodynamic Curves

ABSTRACTThe purpose of this study was to characterize KOH based electrolytes and effects of additives on electro-chemical mechanical planarization. The electrochemical mechanical polisher was made to measure the potentiodynamic curve and removal rate of Cu. The potentiodynamic curves were measured in static and dynamic states in investigated electrolytes using a potentiostat. Cu disk of 2 inch was used as a working electrode and Pt electroplated platen was used as a counter electrode. KOH was used as the electrolyte. H2O2 and citric acid were used as additives for the ECMP of Cu. In static and dynamic potentiodynamic measurements, the corrosion potential decreased and corrosion current increased as a function of KOH concentration. In dynamic state, different potentiodynamic curve was obtained when compared to the static state. The current density did not decrease in passivation region by mechanical polishing effect. The static etch and removal rate were measured as function of KOH concentration and applied voltage. In ECMP system, polishing was performed at 30 rpm and 1 psi. The removal rate was about 60 nm/min at 0.3 V when 5 wt% KOH was used. Also, the effect of additive was investigated in KOH based electrolyte on removal rates. As a result, The removal rate was increased to 350 nm/min when 5wt% KOH, 5vol% H2O2, 0.3 M citric acid were used.

Planarization of Copper Damascene Interconnects by Spin-Etch Process: A Chemical Approach

2000 ◽  
Vol 612 ◽  
Author(s):  
Shyama P. Mukherjee ◽  
Joseph A. Levert ◽  
Donald S. Debear
Keyword(s):  
Fluid Flow ◽  
Process Parameters ◽  
Removal Rate ◽  
Normal Load ◽  
Chemical Mechanical Planarization ◽  
Copper Interconnects ◽  
Primary Process ◽  
Technical Parameters ◽  
Controllable Process ◽  
Damascene Interconnects

ABSTRACTThe present work describes the process principles of “Spin-Etch Planarization” (SEP), an emerging method of planarization of dual damascene copper interconnects. The process involves a uniform removal of copper and the planarization of surface topography of copper interconnects by dispensing abrasive free etchants to a rotating wafer. The primary process parameters comprise of (a) Physics and chemistry of etchants, and (b) Nature of fluid flow on a spinning wafer. It is evident, that unlike conventional chemical-mechanical planarization, which has a large number of variables due to the presence of pads, normal load, and abrasives, SEP has a smaller number of process parameters and most of them are primary in nature. Based on our preliminary works, we have presented the basic technical parameters that contribute to the process and satisfy the basic requirements of planarization such as (a) Uniformity of removal (b) Removal rate (c) Degree of Planarization (d) Selectivity. The anticipated advantages and some inherent limitations are discussed in the context of process principles. We believe that when fully developed, SEP will be a simple, predictable and controllable process.

scholarly journals Wafer Level Packaging Technology Applied to Pixel Detectors

2021 ◽  
Vol 9 ◽  
Author(s):  
Paolo Conci ◽  
Giovanni Darbo ◽  
Andrea Gaudiello ◽  
Claudia Gemme ◽  
Stefano Girardi ◽  
...  
Keyword(s):  
High Energy Physics ◽  
High Energy ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Technical Requirements ◽  
Pixel Detectors ◽  
Single Sensor ◽  
Wafer Processing ◽  
Wafer Level Package ◽  
Energy Physics

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

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