Measurements of interface state density in partially- and fully-depleted silicon-on-insulator MOSFETs by a high-low-frequency transconductance method

1993 ◽  
Vol 33 (9) ◽  
pp. 1435
Keyword(s):  
Low Frequency ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Silicon On Insulator ◽  
Fully Depleted

Heterojuncion Study of Ga0.92In08as(P+)/GaAs(n) Diodes: Correlation of Electrical and Strucrural Characteristics

1989 ◽  
Vol 160 ◽  
Author(s):  
Y.W. Choi ◽  
C.R. Wie ◽  
K.R. Evans ◽  
C.E. Stutz
Keyword(s):  
Low Frequency ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Trap Level ◽  
Fermi Level Pinning ◽  
Pinning Effect ◽  
Quasi Fermi Level ◽  
Current Voltage ◽  
Capacitance Voltage

AbstractDifferent in-plane mismatch was introduced by varying the Ga 0.92In0.08As(p+) epilayer thickness (h-0.1, 0.25, 0.5 and lum) on GaAs(n)/GaAs(n+) structure. For sample with h-lum, quasi-Fermi level pinning effect was observed in low temperature forward Current-Voltage characteristic due to high density misfit dislocation. From Vint measurement at low frequency limit in C-2 vs Voltage plot, interface state density Nss was obtained. From Capacitance-Voltage measurements at different frequencies, single-level interface state density Ns was estimated using Schokley-Read-Hall statistics. Both Nss and Ns show their linear relation with epilayer in-plane mismatch. Admittance Spectroscopy shows an interface trap level at about Ev + 0.36 eV with the hole capture cross section cp = 2.7×10-15 cm-2 for the h-lum sample, and at Ev + 0.21 eV with cP = 2.4×10-16 cm-2 for the h-0.5um sample.

Interface-State-Density Evaluation of p-type and n-type Ge/GeNx Structures by Conductance Technique

2013 ◽  
Vol 133 (7) ◽  
pp. 1279-1284
Author(s):  
Takuro Iwasaki ◽  
Toshiro Ono ◽  
Yohei Otani ◽  
Yukio Fukuda ◽  
Hiroshi Okamoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Conductance Technique ◽  
Density Evaluation ◽  
P Type

Identification of Charging Effects in Plasma-Enhanced TEOS Deposition with Non-Contact Test Techniques

1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson
Keyword(s):  
Vapor Deposition ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Wafer Surface ◽  
Oxide Charge ◽  
Contact Test ◽  
Deposition Power ◽  
Oxide Deposition

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.

scholarly journals Preparation and Characterization of Nitridation Layer on 4H SiC (0001) Surface by Direct Plasma Nitridation

2014 ◽  
Vol 778-780 ◽  
pp. 631-634 ◽  
Author(s):  
Yoshiyuki Akahane ◽  
Takuo Kano ◽  
Kyosuke Kimura ◽  
Hiroki Komatsu ◽  
Yukimune Watanabe ◽  
...  
Keyword(s):  
Interface State ◽  
Nitride Layer ◽  
State Density ◽  
Interface State Density ◽  
Process Temperature ◽  
Pure Nitrogen ◽  
Interface Property ◽  
Plasma Nitridation

A nitride layer was formed on a SiC surface by plasma nitridation using pure nitrogen as the reaction gas at the temperature from 800°C to 1400°C. The surface was characterized by XPS. The XPS measurement showed that an oxinitride layer was formed on the SiC surface by the plasma nitridation. The high process temperature seemed to be effective to activate the niridation reaction. A SiO2film was deposited on the nitridation layer to form SiO2/nitride/SiC structure. The interface state density of the SiO2/nitride/SiC structure was lower than that of the SiO2/SiC structure. This suggested that the nitridation was effective to improve the interface property.

The Properties Of a-Si:H/c-Si Heterostructures Prepared By 55 kHz Pecvd For Solar Cell Application

1997 ◽  
Vol 485 ◽  
Author(s):  
B. G Budaguan ◽  
A. A. Aivazov ◽  
A. A. Sherchenkov ◽  
A. V Blrjukov ◽  
V. D. Chernomordic ◽  
...  
Keyword(s):  
Crystalline Silicon ◽  
Low Frequency ◽  
Reverse Current ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Solar Cell Application ◽  
Current Voltage ◽  
Frequency Plasma ◽  
Device Applications

AbstractIn this work a-Si:H/c-Si heterostructures with good electronic properties of a-Si:H were prepared by 55 kHz Plasma Enhanced Chemical Vapor Deposition (PECVD). Currentvoltage and capacitance-voltage characteristics of a-Si:H/c-Si heterostructures were measuredto investigate the influence of low frequency plasma on the growing film and amorphous silicon/crystalline silicon boundary. It was established that the interface state density is low enough for device applications (<2.1010 cm−2). The current voltage measurements suggest that, when forward biased, space-charge-limited current determines the transport mechanism in a- Si:H/c-Si heterostructures, while reverse current is ascribed to the generation current in a-Si:H and c-Si depletion layers.

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