Electrical mechanisms of bi-stable memory devices based on an Al/PVK:ZnO NPs/ITO structure with different ZnO NPs annealing temperatures

2016 ◽  
Vol 16 (10) ◽  
pp. 1418-1423 ◽  
Author(s):  
Korakot Onlaor ◽  
Natpasit Chaithanatkun ◽  
Benchapol Tunhoo
Keyword(s):  
Memory Devices ◽  
Zno Nps ◽  
Annealing Temperatures ◽  
Stable Memory

Thermally stable memory devices using graphene flakes sandwiched polymethyl methacrylate polymer layers

2012 ◽  
Vol 8 (6) ◽  
pp. 649-653 ◽  
Author(s):  
S. Valanarasu ◽  
A. Kathalingam ◽  
V. Senthilkumar ◽  
V. Kannan ◽  
J. K. Rhee
Keyword(s):  
Polymethyl Methacrylate ◽  
Memory Devices ◽  
Thermally Stable ◽  
Polymer Layers ◽  
Graphene Flakes ◽  
Stable Memory

scholarly journals Characterizing Synchronous Writes in Stable Memory Devices

2019 ◽  
Author(s):  
William B. Mingardi ◽  
Gustavo M. D. Vieira
Keyword(s):  
Distributed Algorithms ◽  
Random Access ◽  
File Systems ◽  
Buffer Size ◽  
Memory Devices ◽  
Recovery Model ◽  
Profile Data ◽  
Storage Devices ◽  
Storage Technologies ◽  
Stable Memory

Distributed algorithms that operate in the fail-recovery model rely on the state stored in stable memory to guarantee the irreversibility of operations even in the presence of failures. The performance of these algorithms lean heavily on the performance of stable memory. Current storage technologies have a defined performance profile: data is accessed in blocks of hundreds or thousands of bytes, random access to these blocks is expensive and sequential access is somewhat better. File system implementations hide some of the perfor- mance limitations of the underlying storage devices using buffers and caches. However, fail-recovery distributed algorithms bypass some of these techniques and perform synchronous writes to be able to tolerate a failure during the write itself. Assuming the distributed system designer is able to buffer the algorithm’s writes, we ask how buffer size and latency complement each other. In this paper we start to answer this question by characterizing the performance (throughput and latency) of typical stable memory devices using a representative set of current file systems.

Epitaxial ferroelectric thin films

1994 ◽  
Vol 52 ◽  
pp. 572-573
Author(s):  
S. G. Ghonge ◽  
E. Goo ◽  
R. Ramesh ◽  
R. Haakenaasen ◽  
D. K. Fork
Keyword(s):  
Single Crystal ◽  
Work Function ◽  
Nonvolatile Memory ◽  
Ferroelectric Properties ◽  
Electrical Contact ◽  
Memory Devices ◽  
Ferroelectric Films ◽  
Si Substrates ◽  
Electro Optic ◽  
Wide Range

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.

Adaptive Interference Mitigation for Multilevel Flash Memory Devices

2011 ◽  
Vol E94-A (11) ◽  
pp. 2453-2457
Author(s):  
Myeongwoon JEON ◽  
Kyungchul KIM ◽  
Sungkyu CHUNG ◽  
Seungjae CHUNG ◽  
Beomju SHIN ◽  
...  
Keyword(s):  
Flash Memory ◽  
Interference Mitigation ◽  
Memory Devices

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

High-Throughput, Site-Specific Sample Prep of Ultra-Thin TEM Lamella for Process Metrology and Failure Analysis

2012 ◽  
Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Monitoring ◽  
High Throughput ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Memory Devices ◽  
Site Specific ◽  
Critical Dimensions ◽  
Tem Lamella

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.

Application of Backside Photo and Thermal Emission Microscopy Techniques to Advanced Memory Devices

1997 ◽  
Author(s):  
S.-S. Lee ◽  
J.-S. Seo ◽  
N.-S. Cho ◽  
S. Daniel
Keyword(s):  
Thermal Emission ◽  
Test Cases ◽  
Memory Devices ◽  
Front Side ◽  
Emission Analysis ◽  
Intensity Attenuation ◽  
Analysis Techniques ◽  
Defect Sites ◽  
Emission Microscopy ◽  
Microscopy Techniques

Abstract Both photo- and thermal emission analysis techniques are used from the backside of the die colocate defect sites. The technique is important in that process and package technologies have made front-side analysis difficult or impossible. Several test cases are documented. Intensity attenuation through the bulk of the silicon does not compromise the usefulness of the technique in most cases.

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