Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

2000 ◽  
Vol 49 (3-4) ◽  
pp. 151-168 ◽  
Author(s):  
S. Voldman ◽  
D. Hui ◽  
L. Warriner ◽  
D. Young ◽  
J. Howard ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Cmos Technology ◽  
Copper Interconnects ◽  
Silicon On Insulator ◽  
Esd Protection ◽  
Semiconductor Chips ◽  
Soi Cmos

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Reliability challenge of ESD protection: From planner SOI MOSFET to SOI FinFET

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740004 ◽  
Author(s):  
Yibo Jiang ◽  
Hui Bi ◽  
Liangwei Dong ◽  
Qinglong Li
Keyword(s):  
Electrostatic Discharge ◽  
Silicon On Insulator ◽  
Heat Conductor ◽  
Soi Mosfet ◽  
Novel Device ◽  
Thermal Distribution ◽  
Floating Base ◽  
Esd Protection ◽  
Tcad Simulation ◽  
Soi Technology

Implementation of Electrostatic Discharge (ESD) protection in Silicon on Insulator (SOI) technology is a challenge because of the inherent properties of poor heat conductor and heat trapping. In this paper, a novel device as ESD clamp is proposed as Fix-Base SOI FinFET clamp which addresses the troublesome problem of floating base. Moreover, its manufacturing process is compatible to the normal SOI process flow well. Finally, a detailed discussion including current density and thermal distribution are presented with the technique of 3D TCAD simulation.

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

2008 ◽  
Vol 48 (7) ◽  
pp. 995-999 ◽  
Author(s):  
Xiaoyang Du ◽  
Shurong Dong ◽  
Yan Han ◽  
Juin J. Liou ◽  
Mingxu Huo ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Cmos Technology ◽  
Esd Protection

High Temperature Characterization up to 450 °C of MOSFETs and basic circuits realized in a Silicon-on-Insulator (SOI) CMOS-Technology

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000227-000232
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Output Voltage ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Circuit Function ◽  
Soi Cmos

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. Silicon-on-Insulator-technologies are commonly used up to 250 °C. In this work we evaluate the limit for electronic circuit function realized in thin film SOI-technologies for even higher temperatures. At Fraunhofer IMS a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metalization with excellent reliability concerning electromigration, voltage independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of NMOSFET- and PMOSFET-transistors were studied up to 450 °C. In a second step we investigated the functionality of ring oscillators, representing digital circuits, and bandgap references as examples of simple analog components. The frequency and the current consumption of ring oscillators and the output voltage of bandgap references were also characterized up to 450 °C. We found that the ring oscillator still functions at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the bandgap reference is in the specified range up to 250 °C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS-technology to its real maximum temperature limits.

Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

2014 ◽  
Vol 687-691 ◽  
pp. 3251-3254
Author(s):  
Zhuo Tian ◽  
Bai Cheng Li
Keyword(s):  
Cmos Technology ◽  
Alpha Particles ◽  
Soft Error ◽  
Silicon On Insulator ◽  
Low Power Consumption ◽  
Protection Device ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Soi Technology

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

High Temperature Characterization up to 450°C of MOSFETs and Basic Circuits Realized in a Silicon-on-Insulator (SOI) CMOS Technology

2013 ◽  
Vol 10 (2) ◽  
pp. 67-72 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Band Gap ◽  
Output Voltage ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Soi Cmos

Standard bulk CMOS technology targets operating temperatures of not more than 175°C. Silicon-on-insulator technologies are commonly used up to 250°C. In this work, we evaluate the limit for electronic circuit function realized in thin film SOI technologies for even higher temperatures. At Fraunhofer IMS, a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metallization with excellent reliability concerning electromigration, as well as voltage-independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of an NMOSFET transistor and a PMOSFET transistor are studied up to 450°C. In a second step, we investigate the functionality of a ring oscillator (representing a digital circuit) and a band gap reference as an example of a simple analog component. The frequency and the current consumption of the ring oscillator, as well as the output voltage and the current of the band gap reference, are characterized up to 450°C. We find that the ring oscillator still oscillates at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the band gap reference is in the specified range (change < 3%) up to 250°C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS technology to its real maximum temperature limits.

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