Monolithic multi-phase LC-VCO in ultra-thin silicon-on-insulator (UTSi/spl reg/-SOI) CMOS technology

2003 ◽  
Author(s):  
Liping Zhang ◽  
A.A. Sawchuk
Keyword(s):  
Cmos Technology ◽  
Silicon On Insulator ◽  
Thin Silicon ◽  
Multi Phase ◽  
Lc Vco ◽  
Soi Cmos

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

High Temperature Characterization up to 450 °C of MOSFETs and basic circuits realized in a Silicon-on-Insulator (SOI) CMOS-Technology

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000227-000232
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Output Voltage ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Circuit Function ◽  
Soi Cmos

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. Silicon-on-Insulator-technologies are commonly used up to 250 °C. In this work we evaluate the limit for electronic circuit function realized in thin film SOI-technologies for even higher temperatures. At Fraunhofer IMS a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metalization with excellent reliability concerning electromigration, voltage independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of NMOSFET- and PMOSFET-transistors were studied up to 450 °C. In a second step we investigated the functionality of ring oscillators, representing digital circuits, and bandgap references as examples of simple analog components. The frequency and the current consumption of ring oscillators and the output voltage of bandgap references were also characterized up to 450 °C. We found that the ring oscillator still functions at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the bandgap reference is in the specified range up to 250 °C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS-technology to its real maximum temperature limits.

High Temperature Characterization up to 450°C of MOSFETs and Basic Circuits Realized in a Silicon-on-Insulator (SOI) CMOS Technology

2013 ◽  
Vol 10 (2) ◽  
pp. 67-72 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Band Gap ◽  
Output Voltage ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Soi Cmos

Standard bulk CMOS technology targets operating temperatures of not more than 175°C. Silicon-on-insulator technologies are commonly used up to 250°C. In this work, we evaluate the limit for electronic circuit function realized in thin film SOI technologies for even higher temperatures. At Fraunhofer IMS, a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metallization with excellent reliability concerning electromigration, as well as voltage-independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of an NMOSFET transistor and a PMOSFET transistor are studied up to 450°C. In a second step, we investigate the functionality of a ring oscillator (representing a digital circuit) and a band gap reference as an example of a simple analog component. The frequency and the current consumption of the ring oscillator, as well as the output voltage and the current of the band gap reference, are characterized up to 450°C. We find that the ring oscillator still oscillates at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the band gap reference is in the specified range (change < 3%) up to 250°C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS technology to its real maximum temperature limits.

A half-micron CMOS technology using ultra-thin silicon on insulator

2002 ◽  
Author(s):  
P.H. Woerlee ◽  
C. Juffermans ◽  
H. Lifka ◽  
W. Manders ◽  
F.M.O. Lansink ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Silicon On Insulator ◽  
Thin Silicon

scholarly journals High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

2020 ◽  
Vol 10 (3) ◽  
pp. 27
Author(s):  
Andrea Ballo ◽  
Alfio Dario Grasso ◽  
Salvatore Pennisi ◽  
Chiara Venezia
Keyword(s):  
Resonant Frequency ◽  
Performance Optimization ◽  
Cmos Technology ◽  
Second Order ◽  
Silicon On Insulator ◽  
Circuit Performance ◽  
Fully Depleted ◽  
Current Consumption ◽  
28 Nm ◽  
Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

scholarly journals A 4-mW Temperature-Stable 28 GHz LNA with Resistive Bias Circuit for 5G Applications

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1225
Author(s):  
Dongze Li ◽  
Qingzhen Xia ◽  
Jiawei Huang ◽  
Jinwei Li ◽  
Hudong Chang ◽  
...  
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Gain Variation ◽  
Measurement Results ◽  
Noise Amplifier ◽  
Bias Point ◽  
Soi Cmos

This paper presents a low power two-stage single-end (SE) 28 GHz low-noise amplifier (LNA) in 90 nm silicon-on-insulator (SOI) CMOS technology for 5G applications. In this design, the influence of bias circuit is discussed. The 1200 Ω resistor which was adopted in bias circuit can feed DC voltage as well as keep whole circuit unconditionally stable. The gate bias points are set to 0.55 V to make the circuit low-power and temperature-stable. Measurement results illustrated that the LNA achieved a maximum small signal gain of 18.1 dB and an average 3.1 dB noise figure (NF) in operating frequency band. Measured S11 was below −10 dB between 25 GHz and 29 GHz and reverse isolation S12 was below −25 dB throughout the band. It consumed only 4 mW by proper selection of bias point with core area of 0.16 mm2 without pads. The fabricated LNA has demonstrated a gain variation of 3 dB and a NF variation of 1.9 dB from −40 °C to 125 °C with power variation of 0.8 mW. It suggests that the proposed SOI CMOS LNA can be a promising candidate for 5G applications.

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