Reactions at metal-semiconductor interfaces

Author(s):  
Robert Sinclair

Examination of the architecture of a semiconductor-based microelectronics device shows that metallic, highly conductive components are an integral part of the miniature circuits. As geometries become increasingly small (e.g. at the sub-micron level) the structure at critical interfaces influences the electrical performance to a greater extent. Accordingly metal-semiconductor junctions have significant technological importance, in addition to any natural scientific interest associated with the bonding of two unlike materials. This article reviews some of our recent work on this topic, with particular emphasis on the reactions which can occur either during fabrication of the interface or upon heating in conjunction with device processing or prolonged service.The simplest system consists of an elemental metal and an elemental semiconductor, silicon being the most important example of the latter. Consideration of phase equilibria indicates that such an interface is thermodynamically unstable: upon heating either a reaction can occur to produce a compound phase (i.e. a silicide), or mutual dissolution of the elements within each other takes place to achieve saturated solid solution compositions. Reference to the appropriate binary phase diagram allows prediction of the result if local equilibrium is achieved. Thus although an atomically abrupt metal-semiconductor interface might be grown under specialized circumstances, this situation can be expected to be unusual and moreover it is not stable to elevated temperatures when atomic mobility and diffusion are rapid.

Author(s):  
Heng-Sheng Huang ◽  
Ping-Ray Huang ◽  
Mu-Chun Wang ◽  
Shuang-Yuan Chen ◽  
Shea-Jue Wang ◽  
...  

A novel drive current model covering the effects of source/drain voltage (VDS) and gate voltage (VGS) and incorporating drift and diffusion current on the surface channel at the nano-node level, especially beyond 28nm node is presented. The effect of the diffusion current added is more satisfactory to describe the behavior of the drive current in nano-node MOSFETs, fabricated with the atomic-layer-deposition (ALD) technology. This breakthrough in model establishment can expose the long and short channel devices together. Introducing the variables of VDS and VGS, the mixed current model more effectively and meaningfully demonstrates the drive current of MOSFETs under the operation of horizontal, vertical, or mixed electrical field. In comparison between the simulation and experimental consequences, the electrical performance is impressive. The error between both is less than 1%, better than the empirical adjustment to issue a set of drive current models.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000148-000153
Author(s):  
Karl Malachowski ◽  
Karen Qian ◽  
Maaike Op de Beeck ◽  
Rita Verbeeck ◽  
George Bryce ◽  
...  

Material selection is the key issue when developing a biocompatible packaging process for implantable electronic systems. To secure a reliable performance of the chip in such a package, its encapsulation has to be considered up-front in the wafer-level integration scheme. A differentiation of two main material types can be made:1) Insulating or passive materials functioning as a bi-directional diffusion barrier preventing body fluids leaking into the package causing systems malfunction due to possible materials corrosion and also avoiding a leakage of built-in materials to the in-vivo environment and2) Conductive or active materials as diffusion barriers, e.g. against copper diffusion or as direct external contacts responsible for electrical performance of the system. This study investigates the properties of two widely used insulating materials in the semiconductor industry, the nitride and the oxide. Both material types are deposited in a PECVD system using different temperatures; 400 ° C for CMOS compatibility and 200 ° C for wafer back side process integration when a temporary carrier system is used. The biocompatibility investigations of these materials (evaluated using cell lines and primary cells) show promising results. However, for the long term application, the stability results for the oxide layers show hydration effects resulting in material degradation where the nitride layers clearly show corrosion and are even etched when elevated temperatures are applied. This fact is surprising since nitride layers are widely used as a humidity barrier for various chip types but obviously not suitable for a direct contact with liquids. Various analysis methods using e.g. Fourier Transformed IR Spectroscopy or mass measurements substantiate this thesis.


2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000033-000036 ◽  
Author(s):  
M.H. Weng ◽  
A.D. Murphy ◽  
D.T. Clark ◽  
D.A. Smith ◽  
R.F. Thompson ◽  
...  

The potential to thermally grow SiO2 on silicon carbide has resulted in it becoming the technology of choice to realise high temperature CMOS circuits. The challenge to achieve a high quality gate stack relies on engineering the metal-insulator-semiconductor interfaces to enable reliable high temperature functionality. Here we describe the effect of different process conditions for the formation of the dielectric layer on the characteristics of the resulting devices. The operating characteristics at elevated temperatures depend critically on the quality of the gate stack. Therefore a systematic evaluation of the intrinsic properties of the gate stack and data from reliability tests are needed.


2019 ◽  
Vol 54 (20) ◽  
pp. 13420-13432 ◽  
Author(s):  
Shiyi Wen ◽  
Yong Du ◽  
Yuling Liu ◽  
Peng Zhou ◽  
Zi-kui Liu

2019 ◽  
Vol 9 (23) ◽  
pp. 5014
Author(s):  
Courtin ◽  
Moréac ◽  
Delhaye ◽  
Lépine ◽  
Tricot ◽  
...  

Fermi level pinning at metal/semiconductor interfaces forbids a total control over the Schottky barrier height. 2D materials may be an interesting route to circumvent this problem. As they weakly interact with their substrate through Van der Waals forces, deposition of 2D materials avoids the formation of the large density of state at the semiconductor interface often responsible for Fermi level pinning. Here, we demonstrate the possibility to alleviate Fermi-level pinning and reduce the Schottky barrier height by the association of surface passivation of germanium with the deposition of 2D graphene.


2001 ◽  
Vol 679 ◽  
Author(s):  
Carrie Daniels-Hafer ◽  
Meehae Jang ◽  
Frank E. Jones ◽  
Shannon W. Boettcher ◽  
Rob Danner ◽  
...  

ABSTRACTThe n-InP | poly(pyrrole) interface is used as a case study to discuss the calculation of the transmission coefficient, describing the probability of majority carrier transfer, at a non-ideal semiconductor interface exhibiting anomalous behavior assumed to be due to a spatial distribution of barrier heights. The most notable anomaly is a weaker dependence of current on voltage than predicted by thermionic emission (i.e. quality or ideality factor greater than unity). Central to this discussion is the calculation of the equilibrium exchange current density Jo and barrier height Φb in light of a heterogeneous and potentially voltage-dependent barrier distribution. Various approaches to the measurement of Φb and Jovalid for semiconductor interfaces characterized by a uniform, voltage- and temperature-independent barrier are discussed when applied to a heterogeneous interface. In particular, the use of a capacitance-voltage measured barrier is demonstrated to result in an overestimation of κ whereas the use of a Richardson plot barrier is demonstrated to result in an underestimation. Depending on method, errors in excess of five orders-of-magnitude are observed for the n-InP | poly(pyrrole) interface under conditions where it exhibits only mildly anomalous behavior (ideality factor ≍ 1.2). The greatest confidence in the transmission coefficients occurs when the ideality factor is unity and the capacitance-voltage barrier agrees with the Richardson Plot barrier.


2014 ◽  
Vol 622-623 ◽  
pp. 508-513
Author(s):  
Yong Nam Kwon ◽  
S.S. Hong ◽  
H.G. Kim

Superplastic forming has been known for the ideal process for manufacturing complex parts. Also, diffusion bonding can give a higher design flexibility, which allows a better performance with a lower overall manufacturing cost. Fine grained INCONEL 718 alloy sheet has been known to show superplastic behavior with the combination of high strength and corrosion resistance at the elevated temperatures. In the present study, high temperature deformation characteristic of INCONEL 718 sheet with 15m was investigated firstly. Then, blow forming process with cylindrical cavity was tried. Also, best diffusion brazing and bonding condition was tried to be defined in terms of temperature, pressure and time. Bonding strength was characterized by using lap shear type test and interface observation. Characteristics of deformation and diffusion bonding at high temperature were influenced greatly with grain size while Nb precipitate also played an important role.


1997 ◽  
Vol 483 ◽  
Author(s):  
J. C. Zolperw

AbstractJunction field effect transistors (JFETs) are attractive for high-temperature or highpower operation since they rely on a buried semiconductor junction, and not a metal semiconductor interface as in a metal semiconductor (MESFET) or heterojunction field effect transistor (HFET), for modulating the transistor channel. This is important since a metal/semiconductor interface often degrades at elevated temperatures, either due to the ambient temperature or to Joule heating at high current levels, while a buried semiconductor junction can withstand higher temperatures. In fact, for proper design, the JFET becomes limited by thermal carrier generation in the semiconductor and not metallurgical degradation of the gate electrode.In this talk an overview is given of JFET technology based on GaAs, SiC, and GaN. While impressive room temperature, high-frequency, results have been reported for GaAs JFET's with unit current gain cut-off frequencies up to 50 GHz, more work is needed to limit substrate conduction for optimum operation at 300 °C and above. For SiC JFETs, well behaved transistor operation has been maintained up to 600 °C, however, increased frequency performance is needed. More recently, a GaN JFET has also been demonstrated that is promising for similarly high temperature operation but is presently limited by buffer conduction. Future directions for each of these technologies, and potential extension to high power switching devices such as thyristors, will be presented at the conference.


2008 ◽  
Vol 138 ◽  
pp. 91-118 ◽  
Author(s):  
Yuriy S. Nechaev

Specific phase transitions to the compound-like impurity nanosegregation structures at dislocations and grain boundaries in metals and their influence on diffusion-assisted processes are considered, mainly, on the basis of the thermodynamic analysis of the related experimental data. The following systems and aspects are in detail considered: (1) the hydride-like nanosegregation of hydrogen at dislocations and grain boundaries in palladium and their influence on the apparent characteristics of hydrogen solubility and diffusivity in palladium; (2) the physics of the anomalous characteristics of diffusion of Fe and other transition impurities in crystalline Al at elevated temperatures, the role of the compound-like nanosegregation (CLNS) of Fe and the others at dislocations and grain boundaries in Al, analysis of the Mössbauer and diffusion data on CLNS of Fe at grain boundaries and dislocations in Al; (3) some new physical aspects of internal oxidation and nitridation of metals (for Cu-0.3%Fe alloy/Cu2O surface layer, and for (Ni-5%Cr) alloy / N2 gas), the role of the compound-like impurity nanosegregation at dislocations and grain boundaries, study results on the deviations from the classical theories predictions and their interpretation. The possibility is considered of nanotechnology applications of the study results for creation of nanostructured metals with compound-like nanosegregation structures at grain boundaries, in order to obtain specific physical and mechanical properties of such a cellural-type nanocomposites. In particular, it can be complex hydride-like, carbide-like, nitride-like, carbide-nitride-like, oxide-like or intermetallide-like nanosegregation structures at grain boundaries of nanostructured metals.


2021 ◽  
Vol 21 (7) ◽  
pp. 3847-3852
Author(s):  
Do-Kyung Kim ◽  
Jihwan Park ◽  
Premkumar Vincent ◽  
Jun-Ik Park ◽  
Jaewon Jang ◽  
...  

Top-gate amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are designed with numerical analysis to control their electron potential energy. Design simulations show the effects of structural design on the electrical characteristics of these TFTs. In particular, the thicknesses of the channel (tch) and conducting (tc) layers, which play vital roles in TFT electrical performance, are varied from 1 to 50 nm to investigate the effect of thicknesses on the electron potential energies of the channel region and the electrode-semiconductor interfaces. The potential energies are precisely optimized for efficient charge transport, injection, and extraction, thus enhancing the electrical performance of these devices. It is also demonstrated that tch mainly affects mobility and threshold voltage, while tc mainly affects on-current. An acceptable threshold voltage of 0.55 V and high mobility of 14.7 cm2V−1s−1 are obtained with a tch of 30 nm and tc of 10 nm. Controllability of the electron potential energies and electrical performance of IGZO TFTs by means of structural design will contribute to realization of next-generation displays that have large areas and high resolutions.


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