A Novel Electrical Test by C-AFM to Differentiate Gate-to-S/D Gate Oxide Short From Non-Gate Oxide Short Defect in Real Products

2004 ◽  
Author(s):  
Cheng-Piao Lin ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting
Keyword(s):  
Atomic Force Microscopy ◽  
Short Path ◽  
Gate Oxide ◽  
Electrical Test ◽  
Force Microscopy ◽  
Atomic Force ◽  
Gate Oxide Short ◽  
Voltage Contrast

Abstract A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.

Gate Oxide Defect Localization and Analysis by Using Conductive Atomic Force Microscopy

2005 ◽  
Author(s):  
Z. H. Lee ◽  
C. J. Lin ◽  
S. W. Lai ◽  
J. H. Chou
Keyword(s):  
Atomic Force Microscopy ◽  
Case Studies ◽  
Gate Oxide ◽  
Wet Etching ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
Defect Localization ◽  
Different Types ◽  
Voltage Contrast

Abstract This paper describes gate oxide defect localization and analysis using passive voltage contrast (PVC) and conductive atomic force microscopy (C-AFM) in a real product through two case studies. In this paper, 10% wt KOH was used to etch poly-Si and expose gate oxide. In the case studies, different types of gate oxide defects will cause different leakage paths. According to the I-V curve measured by C-AFM, we can distinguish between short mode and gate oxide related leakage. For gate oxide leakage, KOH wet etching was successfully used to identify the gate oxide pinholes.

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

2003 ◽  
Author(s):  
Jon C. Lee ◽  
J. H. Chuang
Keyword(s):  
Atomic Force Microscopy ◽  
Integrated Circuits ◽  
Fault Localization ◽  
Electrical Characterization ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
Optical Electron ◽  
Defect Isolation ◽  
Voltage Contrast

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

2006 ◽  
Vol 527-529 ◽  
pp. 1265-1268 ◽  
Author(s):  
Jeffery B. Fedison ◽  
Chris S. Cowen ◽  
Jerome L. Garrett ◽  
E.T. Downey ◽  
James W. Kretchmer ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
High Temperature ◽  
Room Temperature ◽  
Gate Oxide ◽  
Surface Roughening ◽  
Force Microscopy ◽  
Atomic Force ◽  
N Source ◽  
High Temperature Anneal ◽  
Blocking Voltage

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

A Sample Preparation Technique to Localize Gate Oxide Defects in Memory Arrays Using Conducting Atomic Force Microscopy

2011 ◽  
Author(s):  
Lakshminarayanan Lakshmanan ◽  
Lowell Herlinger ◽  
Kathryn Miller
Keyword(s):  
Atomic Force Microscopy ◽  
Sample Preparation ◽  
Gate Oxide ◽  
Silicon On Insulator ◽  
Preparation Technique ◽  
Force Microscopy ◽  
Atomic Force ◽  
Sample Preparation Technique ◽  
Oxide Defects ◽  
Preparation Techniques

Abstract Shrinking gate lengths have led to increased challenges in isolating defects using conventional physical failure analysis methods. Conducting atomic force microscopy (CAFM) has been proven to be a powerful tool to isolate gate oxide defects in silicon-on-insulator devices. Some sample preparation techniques of exposing polysilicon and gate oxide, which were critical to perform CAFM scan, are discussed in this paper.

Novel Gox Inspection Methodology in Advanced Silicon Process

2011 ◽  
Author(s):  
Kuo Yu Wang ◽  
Kuo Hsiung Chen ◽  
Jian Chang Lin ◽  
W. S. Wu
Keyword(s):  
Atomic Force Microscopy ◽  
Leakage Current ◽  
Gate Oxide ◽  
New Method ◽  
Electrical Behavior ◽  
Inspection Method ◽  
Force Microscopy ◽  
Atomic Force

Abstract This paper describes a new gate oxide (Gox) inspection method that uses nanoprobing and capacitive-atomic force microscopy (C-AFM) along with optimized etch chemistries and polishing techniques. It presents several examples showing how the new method outperforms conventional Gox inspection approaches in its ability to locate defects such as oxide pin holes and impurities that cause leakage current. It also discusses the electrical behavior of pin holes and soft defects.

Sign in / Sign up

Export Citation Format

Share Document