scholarly journals High spectro-temporal compression on a nonlinear CMOS-chip

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Ju Won Choi ◽  
Ezgi Sahin ◽  
Byoung-Uk Sohn ◽  
George F. R. Chen ◽  
Doris K. T. Ng ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Photon Absorption ◽  
New Paradigm ◽  
Optical Pulses ◽  
Spectral Compression ◽  
Cmos Chip ◽  
Temporal Compression ◽  
On Chip

AbstractOptical pulses are fundamentally defined by their temporal and spectral properties. The ability to control pulse properties allows practitioners to efficiently leverage them for advanced metrology, high speed optical communications and attosecond science. Here, we report 11× temporal compression of 5.8 ps pulses to 0.55 ps using a low power of 13.3 W. The result is accompanied by a significant increase in the pulse peak power by 9.4×. These results represent the strongest temporal compression demonstrated to date on a complementary metal–oxide–semiconductor (CMOS) chip. In addition, we report the first demonstration of on-chip spectral compression, 3.0× spectral compression of 480 fs pulses, importantly while preserving the pulse energy. The strong compression achieved at low powers harnesses advanced on-chip device design, and the strong nonlinear properties of backend-CMOS compatible ultra-silicon-rich nitride, which possesses absence of two-photon absorption and 500× larger nonlinear parameter than in stoichiometric silicon nitride waveguides. The demonstrated work introduces an important new paradigm for spectro-temporal compression of optical pulses toward turn-key, on-chip integrated systems for all-optical pulse control.

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

2012 ◽  
Vol 3 (4) ◽  
pp. 42-56 ◽  
Author(s):  
Sebastian Höppner ◽  
Dennis Walter ◽  
Georg Ellguth ◽  
René Schüffny
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Error Rates ◽  
Oxide Semiconductor ◽  
Multiprocessor System ◽  
Semiconductor Technology ◽  
Clock Jitter ◽  
Measurement Results ◽  
Delay Variations ◽  
On Chip

This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

scholarly journals A Multiplexed Chemical Sensing CMOS Imager

2021 ◽  
Author(s):  
Di Wang ◽  
Fenni Zhang ◽  
Kyle Mallires ◽  
Vishal Tipparaju ◽  
Jingjing Yu ◽  
...  
Keyword(s):  
Chemical Sensing ◽  
High Performance ◽  
Health Management ◽  
Complementary Metal Oxide Semiconductor ◽  
Spot Size ◽  
Oxide Semiconductor ◽  
Colorimetric Sensing ◽  
Widespread Application ◽  
Cmos Imager ◽  
Cmos Chip

Abstract A miniaturized and multiplexed chemical sensing technology is urgently needed to empower mobile devices, Internet-of-Things (IoTs) and robots for various new applications. Here, we show that a complementary metal-oxide-semiconductor (CMOS) imager can be turned into a multiplexed colorimetric sensing chip by coating micron-scale colorimetric sensing spots on the imager surface. Each sensing spot contains chemical sensing materials and nanoparticles for colorimetric signal enhancement. The sensitivity is spot-size invariant, and high-performance chemical sensing can be achieved on sensing spot as small as ~ 10 µm. This great scalability combined with millions of pixels of a CMOS imager offers a promising platform for highly integrated chemical sensors. Moreover, the chemical CMOS chip can be readily integrated with mobile electronics. As a proof-of-concept, we have built a smartphone accessary based on this chemical CMOS chip for personal health management. We anticipate that this new platform will pave the way for the widespread application of chemical sensing, such as mobile health (mHealth), IoTs, electronic nose, and smart homes.

scholarly journals Integrated silicon carbide modulator for CMOS photonics

2021 ◽  
Author(s):  
Keith Powell ◽  
Liwei Li ◽  
Amirhassan Shams-Ansari ◽  
Jianfu Wang ◽  
Debin Meng ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Oxide Semiconductor ◽  
Photon Absorption ◽  
Stable Operation ◽  
Pockels Effect ◽  
Long Distance ◽  
Optical Carrier

Abstract The electro-optic modulator encodes electrical signals onto an optical carrier, and is essential for the operation of global communication systems and data centers that society demands. An ideal modulator results from scalable semiconductor fabrication and is integrable with electronics. Accordingly, it is compatible with complementary metal-oxide-semiconductor (CMOS) fabrication processes. Moreover, modulators using the Pockels effect enables low loss, ultrafast, and wide-bandwidth data transmission. Although strained silicon-based modulators could satisfy these criteria, fundamental limitations such as two-photon absorption, poor thermal stability and a narrow transparency window hinder their performance. On the other hand, as a wide bandgap semiconductor material, silicon carbide is CMOS compatible and does not suffer from these limitations. Due to its combination of color centers, high breakdown voltage, and strong thermal conductivity, silicon carbide is a promising material for CMOS electronics and photonics with applications ranging from sensors to quantum and nonlinear photonics. Importantly, silicon carbide exhibits the Pockels effect, but a modulator has not been realized since the discovery of this effect more than three decades ago. Here we design, fabricate, and demonstrate the first Pockels modulator in silicon carbide. Specifically, we realize a waveguide-integrated, small form-factor, gigahertz-bandwidth modulator that can operate using CMOS-level drive voltages on a thin film of silicon carbide on insulator. Furthermore, the device features no signal degradation and stable operation at high optical intensities (913 kW/mm2), allowing for high optical signal-to-noise ratios for long distance communications. Our work unites Pockels electro-optics with a CMOS platform to pave the way for foundry-compatible integrated photonics.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

scholarly journals Angular Light, Polarization and Stokes Parameters Information in a Hybrid Image Sensor with Division of Focal Plane

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3391
Author(s):  
Francelino Freitas Carvalho ◽  
Carlos Augusto de Moraes Cruz ◽  
Greicy Costa Marques ◽  
Kayque Martins Cruz Damasceno
Keyword(s):  
Integrated Circuit ◽  
Incident Angle ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Light Polarization ◽  
Oxide Semiconductor ◽  
Stokes Parameters ◽  
New Paradigm ◽  
Depth Sensing ◽  
3D Image Reconstruction

Targeting 3D image reconstruction and depth sensing, a desirable feature for complementary metal oxide semiconductor (CMOS) image sensors is the ability to detect local light incident angle and the light polarization. In the last years, advances in the CMOS technologies have enabled dedicated circuits to determine these parameters in an image sensor. However, due to the great number of pixels required in a cluster to enable such functionality, implementing such features in regular CMOS imagers is still not viable. The current state-of-the-art solutions require eight pixels in a cluster to detect local light intensity, incident angle and polarization. The technique to detect local incident angle is widely exploited in the literature, and the authors have shown in previous works that it is possible to perform the job with a cluster of only four pixels. In this work, the authors explore three novelties: a mean to determine three of four Stokes parameters, the new paradigm in polarization cluster-pixel design, and the extended ability to detect both the local light angle and intensity. The features of the proposed pixel cluster are demonstrated through simulation program with integrated circuit emphasis (SPICE) of the regular Quadrature Pixel Cluster and Polarization Pixel Cluster models, the results of which are compliant with experimental results presented in the literature.

scholarly journals Fully integrated CMOS-compatible polarization analyzer

Nanophotonics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 467-474 ◽  
Author(s):  
Wenhao Wu ◽  
Yu Yu ◽  
Wei Liu ◽  
Xinliang Zhang
Keyword(s):  
Polarization State ◽  
Complementary Metal Oxide Semiconductor ◽  
Polarization Measurement ◽  
Oxide Semiconductor ◽  
Polarization Angle ◽  
Fully Integrated ◽  
Polarization Analyzer ◽  
On Chip ◽  
Easy Integration ◽  
Silicon Based

AbstractPolarization measurement has been widely used in material characterization, medical diagnosis and remote sensing. However, existing commercial polarization analyzers are either bulky schemes or operate in non-real time. Recently, various polarization analyzers have been reported using metal metasurface structures, which require elaborate fabrication and additional detection devices. In this paper, a compact and fully integrated silicon polarization analyzer with a photonic crystal-like metastructure for polarization manipulation and four subsequent on-chip photodetectors for light-current conversion is proposed and demonstrated. The input polarization state can be retrieved instantly by calculating four output photocurrents. The proposed polarization analyzer is complementary metal oxide semiconductor-compatible, making it possible for mass production and easy integration with other silicon-based devices monolithically. Experimental verification is also performed for comparison with a commercial polarization analyzer, and deviations of the measured polarization angle are <±1.2%.

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