scholarly journals Graphene memristive synapses for high precision neuromorphic computing

2020 ◽  
Vol 11 (1) ◽  
Author(s):  
Thomas F. Schranghamer ◽  
Aaryan Oberoi ◽  
Saptarshi Das
Keyword(s):  
Hardware Implementation ◽  
State Of The Art ◽  
Matrix Multiplication ◽  
Multi Level ◽  
Convergence Problems ◽  
Artificial Neural ◽  
Conductance States ◽  
On Chip ◽  
Vector Matrix ◽  
Computing Accuracy

Abstract Memristive crossbar architectures are evolving as powerful in-memory computing engines for artificial neural networks. However, the limited number of non-volatile conductance states offered by state-of-the-art memristors is a concern for their hardware implementation since trained weights must be rounded to the nearest conductance states, introducing error which can significantly limit inference accuracy. Moreover, the incapability of precise weight updates can lead to convergence problems and slowdown of on-chip training. In this article, we circumvent these challenges by introducing graphene-based multi-level (>16) and non-volatile memristive synapses with arbitrarily programmable conductance states. We also show desirable retention and programming endurance. Finally, we demonstrate that graphene memristors enable weight assignment based on k-means clustering, which offers greater computing accuracy when compared with uniform weight quantization for vector matrix multiplication, an essential component for any artificial neural network.

UL-CNN: An Ultra-Lightweight Convolutional Neural Network Aiming at Flash-Based Computing-In-Memory Architecture for Pedestrian Recognition

2020 ◽  
pp. 2150022
Author(s):  
Chen Yang ◽  
Jingyu Zhang ◽  
Qi Chen ◽  
Yi Xu ◽  
Cimang Lu
Keyword(s):  
Neural Network ◽  
Convolutional Neural Network ◽  
Design Methodology ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Memory Architecture ◽  
Storage Overhead ◽  
Speed Up ◽  
Memory Bottleneck ◽  
On Chip

Pedestrian recognition has achieved the state-of-the-art performance due to the progress of recent convolutional neural network (CNN). However, mainstream CNN models are too complicated to emerging Computing-In-Memory (CIM) architectures for hardware implementation, because enormous parameters and massive intermediate processing results may incur severe “memory bottleneck”. This paper proposed a design methodology of Parameter Substitution with Nodes Compensation (PSNC) to significantly reduce parameters of CNN model without inference accuracy degradation. Based on the PSNC methodology, an ultra-lightweight convolutional neural network (UL-CNN) was designed. The UL-CNN model is a specially optimized convolutional neural network aiming at a flash-based CIM architecture (Conv-Flash) and to apply for recognizing person. The implementation result of running UL-CNN on Conv-Flash shows that the inference accuracy is up to 94.7%. Compared to LeNet-5, on the premise of the similar operations and accuracy, the amounts of UL-CNN’s parameters are less than 37% of LeNet-5 at the same dataset benchmark. Such parameter reduction can dramatically speed up the training process and economize on-chip storage overhead, as well as save the power consumption of the memory access. With the aid of UL-CNN, the Conv-Flash architecture can provide the best energy efficiency compared to other platforms (CPU, GPU, FPGA, etc.), which consumes only 2.2[Formula: see text] 105J to complete pedestrian recognition for one frame.

scholarly journals A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2181
Author(s):  
Youngbae Kim ◽  
Shuai Li ◽  
Nandakishor Yadav ◽  
Kyuwon Ken Choi
Keyword(s):  
Neural Networks ◽  
Power Consumption ◽  
Low Power ◽  
State Of The Art ◽  
Cell Structure ◽  
Matrix Multiplication ◽  
Minimum Size ◽  
Cell Array ◽  
Ultra Low Power ◽  
Vector Matrix

We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

scholarly journals Bioengineered Islet Cell Transplantation

2021 ◽  
Author(s):  
Kevin Bellofatto ◽  
Beat Moeckli ◽  
Charles-Henri Wassmer ◽  
Margaux Laurent ◽  
Graziano Oldani ◽  
...  
Keyword(s):  
State Of The Art ◽  
Diabetes Research ◽  
Islet Cell Transplantation ◽  
Β Cell ◽  
Cell Compartment ◽  
Factors Affecting ◽  
Insulin Activity ◽  
On Chip

Abstract Purpose of Review β cell replacement via whole pancreas or islet transplantation has greatly evolved for the cure of type 1 diabetes. Both these strategies are however still affected by several limitations. Pancreas bioengineering holds the potential to overcome these hurdles aiming to repair and regenerate β cell compartment. In this review, we detail the state-of-the-art and recent progress in the bioengineering field applied to diabetes research. Recent Findings The primary target of pancreatic bioengineering is to manufacture a construct supporting insulin activity in vivo. Scaffold-base technique, 3D bioprinting, macro-devices, insulin-secreting organoids, and pancreas-on-chip represent the most promising technologies for pancreatic bioengineering. Summary There are several factors affecting the clinical application of these technologies, and studies reported so far are encouraging but need to be optimized. Nevertheless pancreas bioengineering is evolving very quickly and its combination with stem cell research developments can only accelerate this trend.

scholarly journals Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1589
Author(s):  
Krzysztof Kołek ◽  
Andrzej Firlit ◽  
Krzysztof Piątek ◽  
Krzysztof Chmielowiec
Keyword(s):  
Code Generation ◽  
State Of The Art ◽  
Power Grids ◽  
Practical Implementation ◽  
System A ◽  
Measuring Devices ◽  
Point Representation ◽  
Measurement Algorithm ◽  
On Chip ◽  
Vhdl Code

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

scholarly journals Contextualized Filtering for Shared Cyber Threat Information

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4890
Author(s):  
Athanasios Dimitriadis ◽  
Christos Prassas ◽  
Jose Luis Flores ◽  
Boonserm Kulvatunyou ◽  
Nenad Ivezic ◽  
...  
Keyword(s):  
Information Sharing ◽  
Business Processes ◽  
State Of The Art ◽  
Contextual Information ◽  
Coarse Grained ◽  
Business Information ◽  
Cyber Threat ◽  
Domain Expertise ◽  
Multi Level ◽  
Filtering Approach

Cyber threat information sharing is an imperative process towards achieving collaborative security, but it poses several challenges. One crucial challenge is the plethora of shared threat information. Therefore, there is a need to advance filtering of such information. While the state-of-the-art in filtering relies primarily on keyword- and domain-based searching, these approaches require sizable human involvement and rarely available domain expertise. Recent research revealed the need for harvesting of business information to fill the gap in filtering, albeit it resulted in providing coarse-grained filtering based on the utilization of such information. This paper presents a novel contextualized filtering approach that exploits standardized and multi-level contextual information of business processes. The contextual information describes the conditions under which a given threat information is actionable from an organization perspective. Therefore, it can automate filtering by measuring the equivalence between the context of the shared threat information and the context of the consuming organization. The paper directly contributes to filtering challenge and indirectly to automated customized threat information sharing. Moreover, the paper proposes the architecture of a cyber threat information sharing ecosystem that operates according to the proposed filtering approach and defines the characteristics that are advantageous to filtering approaches. Implementation of the proposed approach can support compliance with the Special Publication 800-150 of the National Institute of Standards and Technology.

scholarly journals Multi-Level Switching of Al-Doped HfO2 RRAM with a Single Voltage Amplitude Set Pulse

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 731
Author(s):  
Jinfu Lin ◽  
Shulong Wang ◽  
Hongxia Liu
Keyword(s):  
Random Access ◽  
Resistive Random Access Memory ◽  
Programming Algorithm ◽  
Voltage Amplitude ◽  
Strength Change ◽  
Value Range ◽  
Multi Level ◽  
Conductance States ◽  
Switching Characteristics ◽  
Sandwiched Structure

In this paper, the resistive switching characteristics in a Ti/HfO2: Al/Pt sandwiched structure are investigated for gradual conductance tuning inherent functions. The variation in conductance of the device under different amplitudes and voltage pulse widths is studied. At the same time, it was found that the variation in switching parameters in resistive random-access memory (RRAM) under impulse response is impacted by the initial conductance states. The device was brought to a preset resistance value range by energizing a single voltage amplitude pulse with a different number of periodicities. This is an efficient and simple programming algorithm to simulate the strength change observed in biological synapses. It exhibited an on/off of about 100, an endurance of over 500 cycles, and a lifetime (at 85 °C) of around 105 s. This multi-level switching two-terminal device can be used for neuromorphic applications to simulate the gradual potentiation (increasing conductance) and inhibition (decreasing conductance) in an artificial synapse.

Freeway Slope Stability Evaluation Based on Multi-Level Fuzzy Neural Network

2012 ◽  
Vol 430-432 ◽  
pp. 1700-1703
Author(s):  
Yan Kai Wu ◽  
Xian Song Sang ◽  
Bin Niu
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Slope Stability ◽  
Basic Principle ◽  
Fuzzy Neural Network ◽  
Stability Assessment ◽  
High Slope ◽  
Fuzzy Neural ◽  
Multi Level ◽  
Artificial Neural

On the basis of introduced basic principle of fuzzy-artificial neural network, this article constructed a slope stability assessment index system with multi-level fuzzy neural network, and made detailed evaluation criterion according to the assessment characteristics of slope stability. Through introducing the basic principle of multi-level comprehensive assessment from fuzzy mathematics and artificial neural network theory, it overcomes the defect of difficult to be quantified in evaluation process of slope stability. Therefore, it can be better to deal with some uncertain problems occurred in the slope stability assessment process, and as much as possible to express all factors influencing slope stability really and objectively. We selected 20 single factor evaluation indexes to assess slope stability based on surveying the high slope stability in Mian county-Ningqiang county freeway section. It took "normal distribution model function" as a membership function to develop a program with the model of fuzzy neural network. Furthermore, we took 30 typical slope examples as training sample to conduct effectiveness test and feedback test for the program. After the precision requirement was met, we used the program to evaluate 21 high slope examples and compared the results with the ones solved by traditional mechanical methods. The coincidence degree by using two kinds of methods to assess the same slope stability is 76.2%.

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