Ultra-low voltage common-mode voltage detector circuit

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

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Low-voltage CMOS GM-C filter with rail-to-rail common-mode voltage

Proceedings of the 39th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1996.588086 ◽

2002 ◽

Cited By ~ 10

Author(s):

Chung-Chih Hung ◽

K. Halonen ◽

V. Porra ◽

M. Ismail

Keyword(s):

Low Voltage ◽

Common Mode ◽

Common Mode Voltage ◽

Rail To Rail

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A Multi-Functional De-Icing Equipment Using Modular Parallel PWM Current Source Converters

E3S Web of Conferences ◽

10.1051/e3sconf/202125601033 ◽

2021 ◽

Vol 256 ◽

pp. 01033

Author(s):

Yang Hu ◽

Heng Zhang ◽

Jing Chen ◽

Huan Zhang ◽

Xinmeng Liu ◽

...

Keyword(s):

Reactive Power ◽

Low Voltage ◽

Current Source ◽

Modulation Method ◽

Switching Frequency ◽

Common Mode ◽

Common Mode Voltage ◽

Current Sharing ◽

Harmonic Elimination ◽

Switching State

For transmission line de-icing, a five level specific harmonic elimination (5l-she) modulation method for high-power parallel current source is proposed, which realizes the current balance of DC bridge arm and the suppression of common mode voltage, and ensures the power quality of grid connected current at low switching frequency. In addition the reactive power of the low voltage load can be compensated at the same time. Firstly, the switching states are classified according to the different mode lengths of PWM current, and the common mode voltage corresponding to each switching state is calculated. Secondly, the current sharing control strategy is established based on the analysis of the influence of redundant switching state on the current sharing of DC bridge arm. Then, the 5l-she waveform is constructed based on the switching state with lower common mode voltage, and the redundant switching states is optimized according to the current sharing strategy. Finally, the effectiveness of the proposed method is verified by simulation.

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An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126615501340 ◽

2015 ◽

Vol 24 (09) ◽

pp. 1550134 ◽

Cited By ~ 1

Author(s):

Seied Zaniar Hoseini ◽

Johar Abdekhoda ◽

Kye-Shin Lee

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Voltage ◽

Average Power ◽

Threshold Region ◽

Clock Frequency ◽

Common Mode ◽

Common Mode Voltage ◽

Sensing Applications ◽

Average Power Consumption

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

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Evaluating Common-Mode Voltage Based Trade-Offs in Differential-Ended and Single-Supplied Signal Conditioning Amplifiers

Electronics ◽

10.3390/electronics10161982 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1982

Author(s):

Marko Petkovsek ◽

Peter Zajec

Keyword(s):

Integrated Circuits ◽

Low Voltage ◽

Reference Voltage ◽

Matched Pair ◽

Signal Conditioning ◽

Voltage Measurement ◽

Common Mode ◽

Common Mode Voltage ◽

Trade Offs ◽

The Impact

This paper focuses on a differential voltage measurement in low-voltage automotive devices whose subunits are separated with a low-side safety switch. In contrast to conventional applications with high-side switches, a common-mode voltage (CMV) with negative polarity exists at the input of the signal conditioning circuitry. To overcome the shortage of dedicated integrated circuits capable of withstanding negative CMV, the paper investigates single- and two-stage differential circuits with single-supplied operational amplifiers to find a cost-optimized counterpart. In addition, the proposed procedure tunes the circuit parameters in such a manner to obtain the largest possible full-scale range at the output. Though, such optimization results in very uncommon values for gain and reference voltages. This issue is additionally evaluated for reference voltages that are either cost-effective or more easily accessible to increase the circuit feasibility. Since the impact of resistances on circuits’ behaviour could be diminished to a great extent using high-precision and matched pair resistors, the sensitivity analysis was investigated only for a reference voltage change. Furthermore, a reversed termination of measured voltages results in a simplified reference voltage selection without hindering circuits’ performance, proven by simulation and experimental results.

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