Increasing market demand for portable high-performance electronic devices is requiring an increase in the I/O density in the chip packaging used to make these products. Flip-chip interconnects that enable advanced packaging utilize a C4 bumping process with lead-free solder to make the chip interconnection. However, with the decreasing chip size and tighter I/O pitch requirements that are needed to realize high-performance, Cu pillar plating has emerged as an enabling technology to meet the technical demands. Cu pillars, capped with a lead-free solder, allow for increased I/O density while still maintaining the standoff needed for proper thermal and electrical performance of stacked chips. With this realized performance, there is expected to be a significant increase in capacity of Cu pillar in the industry, requiring electrolytic Cu plating products with fast deposition rates in order to decrease wafer plating time and increase throughput.
In this paper, Cu electroplating products are evaluated for plating performance at increased deposition rates for Cu pillar applications ranging from micropillar (<20 μm feature size), to standard pillar (20 – 75 μm feature size), redistribution layer (RDL) wiring, and the emerging fan-out wafer level packaging (FO-WLP), which encompasses megapillars (>150 μm feature sizes) as well as stacked via RDL designs. The chief performance criteria for evaluation is the ability to increase deposition rates while maintaining feature height uniformity, smooth and uniform feature morphology, and ability to plate a wide variety of feature sizes and shapes. Additionally, performance of these products is assessed on their ability to plate highly pure Cu deposits which enable void-free integration with lead-free solder without the need of (but is compatible with) a cost-added barrier layer.
