Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000611-000638
Author(s):  
Jonathan Prange ◽  
Yi Qin ◽  
Matthew Thorseth ◽  
Inho Lee ◽  
Masaaki Imanari ◽  
...  

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.

2013 ◽  
Vol 2013 (1) ◽  
pp. 000458-000460
Author(s):  
Jonathan Prange ◽  
Julia Woertink ◽  
Yi Qin ◽  
Pedro Lopez Montesinos ◽  
Inho Lee ◽  
...  

Flip-chip interconnect and 3-D packaging applications must utilize reliable lead-free solder joints in order to produce highly efficient, advanced microelectronic devices. The solder alloy most commonly utilized for these applications is SnAg, which is typically deposited by electroplating due to lower cost and greater reliability as compared to other methods. The electroplating performance and robustness of SnAg products for bumping and capping applications is highly dependent on the organic additives used in the process. Here, next-generation SnAg products that improve the rate of solder electrodeposition without compromising key requirements such as tight Ag% control, uniform height distribution and smooth surface morphology will be discussed. These plated solders were then evaluated for compatibility with bumping, capping and micro-capping applications.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.


2010 ◽  
Vol 146-147 ◽  
pp. 485-490
Author(s):  
Hai Yan Chen ◽  
Xiao Hua Jie ◽  
Hai Yan Zhang ◽  
Yu Long Chen ◽  
Li Guo

Lead-free solder is meeting the requirement of environmental protection, but the property performance of existing lead-free solder is hardly comparable to those of lead solder. In this paper, 0.6% Bi was added into SnXCuNi solder alloy to produce lead-free solder at low cost and high performance. Microstructure, phase composition, melting point, wettability and characteristics of weld interface have been studied and analyzed. The results show that SnXCuNiBi solder alloy are mainly composed of βSn, SnX, Cu6Sn5 and SnBi. The addition of Bi reduces the melting point and improves the wettability of the solder. The main component of the joint interface of SnXCuNiBi/Cu system is Cu6Sn5, which has shown the capability to keep relatively high shear strength at the joint interface.


2004 ◽  
Vol 45 (3) ◽  
pp. 754-758 ◽  
Author(s):  
Ikuo Shohji ◽  
Yuji Shiratori ◽  
Hiroshi Yoshida ◽  
Masahiko Mizukami ◽  
Akira Ichida

2019 ◽  
Vol 14 (1) ◽  
pp. 651-657
Author(s):  
Talita Mazon ◽  
Guilherme E. Prevedel ◽  
Egont A. Schenkel ◽  
Marcio T. Biasoli

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000631-000649
Author(s):  
Matthew A Thorseth ◽  
Mark Scalisi ◽  
Inho Lee ◽  
Sang-Min Park ◽  
Yil-Hak Lee ◽  
...  

Increasing market demand for portable high-performance electronic devices is requiring an increase in the I/O density in the chip packaging used to make these products. Flip-chip interconnects that enable advanced packaging utilize a C4 bumping process with lead-free solder to make the chip interconnection. However, with the decreasing chip size and tighter I/O pitch requirements that are needed to realize high-performance, Cu pillar plating has emerged as an enabling technology to meet the technical demands. Cu pillars, capped with a lead-free solder, allow for increased I/O density while still maintaining the standoff needed for proper thermal and electrical performance of stacked chips. With this realized performance, there is expected to be a significant increase in capacity of Cu pillar in the industry, requiring electrolytic Cu plating products with fast deposition rates in order to decrease wafer plating time and increase throughput. In this paper, Cu electroplating products are evaluated for plating performance at increased deposition rates for Cu pillar applications ranging from micropillar (<20 μm feature size), to standard pillar (20 – 75 μm feature size), redistribution layer (RDL) wiring, and the emerging fan-out wafer level packaging (FO-WLP), which encompasses megapillars (>150 μm feature sizes) as well as stacked via RDL designs. The chief performance criteria for evaluation is the ability to increase deposition rates while maintaining feature height uniformity, smooth and uniform feature morphology, and ability to plate a wide variety of feature sizes and shapes. Additionally, performance of these products is assessed on their ability to plate highly pure Cu deposits which enable void-free integration with lead-free solder without the need of (but is compatible with) a cost-added barrier layer.


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