Design and simulation of electrostatic NEMS logic gates

2018 ◽  
Vol 37 (1) ◽  
pp. 2-28
Author(s):  
P. Pandiyan ◽  
G. Uma ◽  
M. Umapathy
Keyword(s):  
Numerical Simulation ◽  
Computer Aided Design ◽  
Logic Gate ◽  
Beam Theory ◽  
Logic Gates ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Electrode Structure ◽  
Content Type ◽  
Pull Out

Purpose This paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V. Design/methodology/approach The analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE. Findings This paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device. Originality/value The proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

Design and simulation of electro-thermal compliant MEMS logic gates

2018 ◽  
Vol 37 (2) ◽  
pp. 868-889 ◽  
Author(s):  
Pandiyan P. ◽  
Uma G. ◽  
Umapathy M.
Keyword(s):  
Logic Gate ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Micro Electro Mechanical System ◽  
Mechanical Analysis ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Out Of Plane ◽  
Compliant Actuator ◽  
The Given

PurposeThe purpose of this paper is to design an out-of-plane micro electro-thermal-compliant actuator based logic gates which work analogously to complementary metal oxide semiconductor (CMOS) based logic gates. The proposed logic gates used a single-bit mechanical micro ETC actuator per logic instead of using 6-14 individual transistors as in CMOS. Design/methodology/approachA complete analytical modelling is performed on a single ETC vertical actuator, and a relation between the applied voltage and the out-of-plane deflection is derived. Its coupled electro-thermo-mechanical analysis is carried out using micro electro mechanical system (MEMS) CAD tool CoventorWare to illustrate its performance. FindingsThis paper reports analytical and numerical simulation of basic MEMS ETC actuator-based logic gates. The proposed logic gate operates on 5 V, which suits well with conventional CMOS logic, which in turn reduces the power consumption of the device. Originality/valueThe proposed logic gates uses a single-bit MEMS ETC actuator per logic instead of using more transistors as in CMOS. The unique feature of this proposed logic gates is that the basic mechanical ETC actuator is customized in its structure to function as specific logic gates depending upon the given inputs.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

scholarly journals Fermi-level pinning-free WSe2 transistors via 2D van der Waals metal contacts and their complementary logic gate circuits

2021 ◽  
Author(s):  
Jisu Jang ◽  
Hyun-Soo Ra ◽  
Jongtae Ahn ◽  
Tae Wook Kim ◽  
Seung Ho Song ◽  
...  
Keyword(s):  
Fermi Level ◽  
Logic Gate ◽  
Van Der Waals ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Oxide Semiconductor ◽  
Metal Contacts ◽  
Precise Control ◽  
Fermi Level Pinning ◽  
Semiconductor Circuits

Abstract Precise control over the polarity of transistors is a key necessity for the construction of complementary metal–oxide–semiconductor circuits. However, the polarity control of two-dimensional (2D) transistors remains a challenge because of Fermi-level pinning resulting from disorders at metal–semiconductor interfaces. Here, we propose a strategy for clean van der Waals contacts, wherein a metallic 2D material, chlorine-doped SnSe2 (Cl–SnSe2), is used as the contact to provide an interface that is free of defects and Fermi-level pinning. Such clean contacts created via van der Waals integration of a 2D metal possess nearly ideal Schottky barrier heights, thus permitting polarity-controllable transistors. With the integration of 2D metallic Cl–SnSe2 as contacts, WSe2 transistors exhibit pronounced p-type characteristics, which are distinctly different from those of the devices with evaporated metal contacts, where n-type transport is observed. Finally, this ability to control the polarity enables the fabrication of functional logic gates and circuits, including inverter, NAND, and NOR.

Chaotic Laser “Broadcast-Star” Synchronization Network and Its Application in Logic Gates

2019 ◽  
Vol 40 (1) ◽  
pp. 37-50
Author(s):  
Yan Sen Lin
Keyword(s):  
Numerical Simulation ◽  
Semiconductor Laser ◽  
Logic Gate ◽  
Logic Gates ◽  
Practical Implementation ◽  
Input And Output ◽  
Chaotic Laser ◽  
All Optical ◽  
Logic Computation ◽  
Response Systems

Abstract A novel network of “broadcast-star” constituted by a few of injection semiconductor laser cells and its synchronization in chaos are presented to apply in logic gates. Chaotic “broadcast-star” synchronization network is achieved in numerical simulation, where a broadcast using an injected laser drives three response systems with three injected lasers as three “stars” to achieve synchronization between the broadcast and stars while the “stars” obtain synchronization between themselves. The synchronization network model and equation are demonstrated. And logic controlling principle and equation are deduced. We create theoretically the constructions of fundamental gates based on the synchronization network in the “stars” and define their computational principle. Logic gate cell or logic computation can be implemented via controlling logic input and output to the system to synchronize or desynchronize appropriately the chaotic states of twin stars. We present and emulate a lot of all-optical XNOR, NOR, NOT, optoelectronic and combinational optoelectronic logic gates via the optical or optoelectronic modulation while we introduce these logic computational methods. Finally, we analyzed effects of resynchronization and desynchronization on logic detection in a practical implementation of the system. Results show the feasibility of the method.

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

2020 ◽  
Vol 12 (2) ◽  
Author(s):  
Mohamed Zanaty ◽  
Hubert Schneegans ◽  
Ilan Vardi ◽  
Simon Henein
Keyword(s):  
Logic Gate ◽  
Beam Theory ◽  
Logic Gates ◽  
Building Blocks ◽  
Reconfigurable Logic ◽  
Logical Function ◽  
Element Analysis ◽  
Binary Logic ◽  
Geometric Data ◽  
The Stability

Abstract Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this paper, we construct a mechanism to implement a reconfigurable logic gate. This mechanism is based on the concept of programable multistable mechanisms which we introduced in previous work. The application of a programable multistable mechanism is superior to the different bistable mechanisms previously used to implement logic gates since a single mechanism can be used to implement several logic functions. Our reconfigurable logic gates use a novel geometric construction where the geometric data depend on the stability behavior of the mechanism. There are 16 binary logic gates and our construction can theoretically produce nine of these and our physical model produces six logical gates. Input and output of the mechanism are displacement and the mechanisms can be combined serially, i.e., output of a mechanism is an input for another. We show that we can implement nor and nand gates, so combinations of our mechanism can express any logical function. The mechanism is therefore theoretically universal, i.e., implement any computation. We give an analytic model of the mechanism based on Euler–Bernoulli beam theory to find the geometric data, then validate it using finite element analysis and experimental demonstration.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

Structural similitudes of stiffened cylinders

2017 ◽  
Vol 24 (3) ◽  
pp. 527-541 ◽  
Author(s):  
G Petrone ◽  
M Manfredonia ◽  
S De Rosa ◽  
F Franco
Keyword(s):  
Numerical Simulation ◽  
Structural Engineering ◽  
Scaling Laws ◽  
Similarity Theory ◽  
Design Tool ◽  
Engineering Science ◽  
The Finite Element Method ◽  
Engineering Problems ◽  
Incomplete Similarity ◽  
Scaled Models

Similarity theory is a branch of engineering science that deals with establishing conditions of similarity among phenomena and is applied to various fields, such as structural engineering problems, vibration and impact. Tests and numerical simulation of scaled models are still a valuable design tool, whose purpose is to accurately predict the behaviour of large or small prototypes through scaling laws applied to the experimental and numerical results. The aim of this paper is to predict the behaviour of the complete and incomplete similarity of stiffened cylinders by applying distorted scaling laws of the models in similitude. The investigation is performed using models based on the finite element method within commercial software. Two classes of cylinders scaled, with different laws, and, hence, reproducing replicas (exact similitude) and avatars (distorted similitude) are investigated.

The generation of adaptive assembly from predicting change propagation

2015 ◽  
Vol 35 (3) ◽  
pp. 269-280 ◽  
Author(s):  
Hu Qiao ◽  
Rong Mo ◽  
Ying Xiang
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Original Method ◽  
Change Propagation ◽  
Assembly Model ◽  
Practical Application ◽  
Content Type ◽  
Design Structure ◽  
Aided Design ◽  
Practical Implications

Purpose – The purpose of this paper is to establish an adaptive assembly, to realize the adaptive changing of the models and to improve the flexibility and reliability of assembly change. For a three-dimensional (3D) computer-aided design (CAD) assembly in a changing process, there are two practical problems. One is delivering parameters’ information not smoothly. The other one is to easily destroy an assembly structure. Design/methodology/approach – The paper establishes associated parameters design structure matrix of related parts, and predicts possible propagation paths of the parameters. Based on the predicted path, structured storage is made for the affected parameters, tolerance range and the calculation relations. The study combines structured path information and all constrained assemblies to build the adaptive assembly, proposes an adaptive change algorithm for assembly changing and discusses the extendibility of the adaptive assembly. Findings – The approach would improve the flexibility and reliability of assembly change and be applied to different CAD platform. Practical implications – The examples illustrate the construction and adaptive behavior of the assembly and verify the feasibility and reasonability of the adaptive assembly in practical application. Originality/value – The adaptive assembly model proposed in the paper is an original method to assembly change. And compared with other methods, good results have been obtained.

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