Design and simulation of electro-thermal compliant MEMS logic gates

2018 ◽  
Vol 37 (2) ◽  
pp. 868-889 ◽  
Author(s):  
Pandiyan P. ◽  
Uma G. ◽  
Umapathy M.
Keyword(s):  
Logic Gate ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Micro Electro Mechanical System ◽  
Mechanical Analysis ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Out Of Plane ◽  
Compliant Actuator ◽  
The Given

PurposeThe purpose of this paper is to design an out-of-plane micro electro-thermal-compliant actuator based logic gates which work analogously to complementary metal oxide semiconductor (CMOS) based logic gates. The proposed logic gates used a single-bit mechanical micro ETC actuator per logic instead of using 6-14 individual transistors as in CMOS. Design/methodology/approachA complete analytical modelling is performed on a single ETC vertical actuator, and a relation between the applied voltage and the out-of-plane deflection is derived. Its coupled electro-thermo-mechanical analysis is carried out using micro electro mechanical system (MEMS) CAD tool CoventorWare to illustrate its performance. FindingsThis paper reports analytical and numerical simulation of basic MEMS ETC actuator-based logic gates. The proposed logic gate operates on 5 V, which suits well with conventional CMOS logic, which in turn reduces the power consumption of the device. Originality/valueThe proposed logic gates uses a single-bit MEMS ETC actuator per logic instead of using more transistors as in CMOS. The unique feature of this proposed logic gates is that the basic mechanical ETC actuator is customized in its structure to function as specific logic gates depending upon the given inputs.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

Design and simulation of electrostatic NEMS logic gates

2018 ◽  
Vol 37 (1) ◽  
pp. 2-28
Author(s):  
P. Pandiyan ◽  
G. Uma ◽  
M. Umapathy
Keyword(s):  
Numerical Simulation ◽  
Computer Aided Design ◽  
Logic Gate ◽  
Beam Theory ◽  
Logic Gates ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Electrode Structure ◽  
Content Type ◽  
Pull Out

Purpose This paper aims to present a design and simulation of electrostatic nanoelectromechanical system (NEMS)-based logic gates using laterally actuated cantilever with double-electrode structure that can implement logic functions, similar to logic devices that are made of solid-state transistors which operates at 5 V. Design/methodology/approach The analytical modeling of NEMS switch is carried out for finding the pull-in and pull-out voltage based on Euler-Bernoulli’s beam theory, and its numerical simulation is performed using finite element method computer-aided design tool COVENTORWARE. Findings This paper reports analytical and numerical simulation of basic NEMS switch to realize the logic gates. The proposed logic gate operates on 5 V which suits well with conventional complementary metal oxide semiconductor (CMOS) logic which in turn reduces the power consumption of the device. Originality/value The proposed logic gates use a single bit NEMS switch per logic instead of using 6-14 individual transistors as in CMOS. One exclusive feature of this proposed logic gates is that the basic NEMS switch is structurally modified to function as specific logic gates depending upon the given inputs.

scholarly journals Fermi-level pinning-free WSe2 transistors via 2D van der Waals metal contacts and their complementary logic gate circuits

2021 ◽  
Author(s):  
Jisu Jang ◽  
Hyun-Soo Ra ◽  
Jongtae Ahn ◽  
Tae Wook Kim ◽  
Seung Ho Song ◽  
...  
Keyword(s):  
Fermi Level ◽  
Logic Gate ◽  
Van Der Waals ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Oxide Semiconductor ◽  
Metal Contacts ◽  
Precise Control ◽  
Fermi Level Pinning ◽  
Semiconductor Circuits

Abstract Precise control over the polarity of transistors is a key necessity for the construction of complementary metal–oxide–semiconductor circuits. However, the polarity control of two-dimensional (2D) transistors remains a challenge because of Fermi-level pinning resulting from disorders at metal–semiconductor interfaces. Here, we propose a strategy for clean van der Waals contacts, wherein a metallic 2D material, chlorine-doped SnSe2 (Cl–SnSe2), is used as the contact to provide an interface that is free of defects and Fermi-level pinning. Such clean contacts created via van der Waals integration of a 2D metal possess nearly ideal Schottky barrier heights, thus permitting polarity-controllable transistors. With the integration of 2D metallic Cl–SnSe2 as contacts, WSe2 transistors exhibit pronounced p-type characteristics, which are distinctly different from those of the devices with evaporated metal contacts, where n-type transport is observed. Finally, this ability to control the polarity enables the fabrication of functional logic gates and circuits, including inverter, NAND, and NOR.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

A new approach to bypass wire crossing problem in QCA nano technology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy
Keyword(s):  
Power Dissipation ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Nano Technology ◽  
New Approach ◽  
Content Type ◽  
Wire Crossing

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550008 ◽  
Author(s):  
Bander Saman ◽  
P. Mirdha ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. C. Jain ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Proposed Model ◽  
High Band

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

scholarly journals An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

2021 ◽  
Author(s):  
Muhammad Farhan Azmine ◽  
Urmi Debnath ◽  
Yeasir Arafat
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Building Blocks ◽  
Oxide Semiconductor ◽  
Memory Element ◽  
Area Efficiency ◽  
Arithmetic Logic Unit ◽  
Non Volatile Memory ◽  
Electrical Component ◽  
Logic Unit

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

A novel design of nano router with high-speed crossbar scheduler for digital systems in QCA paradigm

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Kalpana Kasilingam ◽  
Paulchamy Balaiah
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Modern Technology ◽  
Oxide Semiconductor ◽  
Large Area ◽  
Content Type ◽  
Compact Size ◽  
High Power Consumption ◽  
High Speed Data

Purpose The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power. Design/methodology/approach In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size. Findings This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area. Research limitations/implications To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler. Practical implications The simulation of the planned circuit with notional information established the practical identity of the scheme. Social implications The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. Originality/value The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.

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