Cleaning control of stencil printing subject to performance deterioration

2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rui Xi ◽  
Jiangyou Yu ◽  
Le Cao ◽  
Xiaojiang Zheng ◽  
Jun Guo
Keyword(s):  
Failure Rate ◽  
System Reliability ◽  
Control Method ◽  
Solder Paste ◽  
Rate Model ◽  
Stencil Printing ◽  
Printing Process ◽  
Content Type ◽  
Printing Quality ◽  
Printing System

Purpose Most solder paste printers are configured to periodically clean the stencil to maintain printing quality. However, a periodical cleaning control may result in excessive cleaning operations. The purpose of this paper is to develop a control method to schedule stencil cleaning operations appropriately. Design/methodology/approach A hybrid failure rate model of the stencil printing process with age reduction factor and failure rate increase factor is presented. A stencil cleaning policy based on system reliability is introduced. An optimization model used to derive the optimal stencil cleaning schedule is provided. Findings An aperiodic stencil cleaning control with good adaptability is achieved. A comparative analysis indicates that aperiodic control has better printing system reliability than traditional periodical control under the same cleaning resource consumption. Originality/value Periodical cleaning control commonly used in industrial printing process often results in excessive cleaning operations. By incorporating the printing system reliability, this paper develops an aperiodic stencil cleaning control method based on hybrid failure rate model of the stencil printing process. It helps to reduce unnecessary cleaning operations while keeping printing quality stable.

The behaviour of solder pastes in stencil printing with electropolishing process

2013 ◽  
Vol 25 (3) ◽  
pp. 164-174 ◽  
Author(s):  
Yong‐Won Lee ◽  
Keun‐Soo Kim ◽  
Katsuaki Suganuma
Keyword(s):  
Circuit Board ◽  
Surface Finishing ◽  
Design Parameters ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Content Type ◽  
Solder Paste Printing ◽  
Solder Mask

PurposeThe purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.Design/methodology/approachDuring the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.FindingsThe results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.Originality/valueDue to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.

A method for optimizing stencil cleaning time in solder paste printing process

2019 ◽  
Vol 31 (4) ◽  
pp. 233-239 ◽  
Author(s):  
JiangYou Yu ◽  
Le Cao ◽  
Hao Fu ◽  
Jun Guo
Keyword(s):  
Decision Model ◽  
Idle Time ◽  
Homogeneous Markov Chain ◽  
Solder Paste ◽  
Quality Loss ◽  
Stencil Printing ◽  
Discrete State ◽  
Printing Process ◽  
Content Type ◽  
Solder Paste Printing

PurposeStencil cleaning is an important operation in solder paste printing process. Frequent cleaning may interrupt printing process and increase idle time, as well as loss for performing cleaning. This paper aims to propose a method to optimize the stencil cleaning time and reduce unnecessary cleaning operations and losses.Design/methodology/approachThis paper uses a discrete-time, discrete-state homogeneous Markov chain to model the stencil printing performance degradation process, and the quality loss during the stencil printing process is estimated based on this degradation model. A stencil cleaning decision model based on renewal reward theorem is established, and the optimal cleaning time is obtained through a balance between quality loss and the loss on idle time.FindingsA stencil cleaning decision model for solder paste printing is established, and numerical simulation results show that there exists an optimal stencil cleaning time which minimizes the long-term loss.Originality/valueStencil cleaning control is very important for solder paste printing. However, there are very few studies focusing on stencil cleaning control. This research contributes to developing a model to optimize the stencil cleaning time in solder paste printing process.

Solder paste volume effects on assembly yield and reliability for bottom terminated components

2017 ◽  
Vol 29 (2) ◽  
pp. 99-109 ◽  
Author(s):  
Sai Srinivas Sriperumbudur ◽  
Michael Meilunas ◽  
Martin Anselm
Keyword(s):  
Thermal Cycling ◽  
Solder Joints ◽  
Inspection System ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Content Type ◽  
Volume Limit ◽  
Solder Paste Printing ◽  
Low Volume

Purpose Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations. Design/methodology/approach Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations. Findings Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling. Originality/value Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Optimising pin-in-paste technology using gradient boosted decision trees

2018 ◽  
Vol 30 (3) ◽  
pp. 164-170 ◽  
Author(s):  
Péter Martinek ◽  
Oliver Krammer
Keyword(s):  
Decision Tree ◽  
Prediction Method ◽  
Percentage Error ◽  
Solder Paste ◽  
Hole Filling ◽  
Decision Tree Learning ◽  
Stencil Printing ◽  
Content Type ◽  
Learning Techniques ◽  
Through Hole

Purpose This paper aims to present a robust prediction method for estimating the quality of electronic products assembled with pin-in-paste soldering technology. A specific board quality factor was also defined which describes the expected yield of the board assembly. Design/methodology/approach Experiments were performed to obtain the required input data for developing a prediction method based on decision tree learning techniques. A Type 4 lead-free solder paste (particle size 20–38 µm) was deposited by stencil printing with different printing speeds (from 20 mm/s to 70 mm/s) into the through-holes (0.8 mm, 1 mm, 1.1 mm, 1.4 mm) of an FR4 board. Hole-filling was investigated with X-ray analyses. Three test cases were evaluated. Findings The optimal parameters of the algorithm were determined as: subsample is 0.5, learning rate is 0.001, maximum tree depth is 6 and boosting iteration is 10,000. The mean absolute error, root mean square error and mean absolute percentage error resulted in 0.024, 0.03 and 3.5, respectively, on average for the prediction of the hole-filling value, based on the printing speed and hole-diameter after optimisation. Our method is able to predict the hole-filling in pin-in-paste technology for different through-hole diameters. Originality/value No research works are available in current literature regarding machine learning techniques for pin-in-paste technology. Therefore, we decided to develop a method using decision tree learning techniques for supporting the design of the stencil printing process for through-hole components and pin-in-paste technology. The first pass yield of the assembly can be enhanced, and the reflow soldering failures of pin-in-paste technology can be significantly reduced.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

scholarly journals Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package

2020 ◽  
pp. 35-38
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez ◽  
Edwin M. Graycochea Jr.
Keyword(s):  
Process Optimization ◽  
Parameter Optimization ◽  
Semiconductor Manufacturing ◽  
Manufacturing Industry ◽  
Solder Ball ◽  
Development Phase ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Centered Ball

One of the challenging assembly processes in semiconductor manufacturing industry is stencil printing using solder paste as direct material. With this technology, some issues were encountered during the development phase of an advanced leadframe device and one of which is the solder ball misplace or off-centered ball. This paper, hence, focused on addressing the ball misplace issue at stencil printing process. Comprehensive parameter optimization particularly on the print speed and print force was employed to eliminate or significantly reduce the ball misplace defect at stencil printing process. With this process optimization and improvement, a reduction of around 96 percent ball misplace occurrence was achieved.

Stencil printing process performance on various aperture size and optimization for lead-free solder paste

2019 ◽  
Vol 102 (9-12) ◽  
pp. 3369-3379 ◽  
Author(s):  
M. S. Rusdi ◽  
M. Z. Abdullah ◽  
S. Chellvarajoo ◽  
M. S. Abdul Aziz ◽  
M. K. Abdullah ◽  
...  
Keyword(s):  
Lead Free ◽  
Lead Free Solder ◽  
Process Performance ◽  
Solder Paste ◽  
Aperture Size ◽  
Stencil Printing ◽  
Printing Process ◽  
Free Solder

Precise solder dispensing in high-throughput micro-device packaging applications

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001284-001294
Author(s):  
Hanzhuang Liang ◽  
Linh Rolland ◽  
Floriana Suriawidjaja ◽  
Mani Ahmadi ◽  
Heakyoung Park
Keyword(s):  
High Throughput ◽  
Smart Phone ◽  
Mesh Size ◽  
Solder Paste ◽  
Mems Devices ◽  
Production Lines ◽  
Stencil Printing ◽  
Content Type ◽  
Packaging Design ◽  
Wide Range

Advanced micro-device packaging sets high and dynamic standard for its supplier industries for speed, precision and flexibility. A high-precision and high-throughput solder paste dispensing process has been developed to fill the gap between novel packaging design and traditional processes of stencil printing and slow dispensing. This process is being used in 25 PCBA production lines to package smart phones, MEMS devices and automobile control panels. These production lines are in full service 24/6 with each dispense system running at 2500unit per hour for simple MEMS patterns, 144uph for complex smart phone patterns and 6uph of full automobile control panels. A well-controlled valve design is applied to achieve high dispensing accuracy at fast speeds. This has removed process design barriers related to dispensing and has matched the high-end platform capability. This process also provides packaging designers with a flexibility superior to the existing solder printing process. The dispense pattern and route can be modified at cost, in minutes and during any step in the design or the assembly stage. Dispensed shapes include dots, lines, rectangle frames and annular rings, with fine edge definition 40um or less. This process can cover a wide range of pattern dimensions between 0.18mm and 100mm. Solder pastes that can be dispensed during this process have 80~90% metal content, type 4 to 6 mesh size. New processes are under development to further push limitations on throughput, dimension, flexibility and material dispensability.

The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components

2016 ◽  
Vol 2016 (1) ◽  
pp. 000667-000674
Author(s):  
Mark Whitmore ◽  
Jeff Schake
Keyword(s):  
Form Factors ◽  
Preliminary Test ◽  
Process Window ◽  
Solder Paste ◽  
Electronic Assembly ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Technology Standard ◽  
The Impact

Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components. In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.

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