The impact of scaling down to deep submicron on CMOS RF circuits

1998 ◽  
Vol 33 (7) ◽  
pp. 1023-1036 ◽  
Author(s):  
Q. Huang ◽  
F. Piazza ◽  
P. Orsatti ◽  
T. Ohguro
Keyword(s):  
Rf Circuits ◽  
Deep Submicron ◽  
Scaling Down ◽  
The Impact ◽  
Cmos Rf

scholarly journals Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru
Keyword(s):  
Process Parameters ◽  
Simulation Analysis ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Device Structure ◽  
Short Channel ◽  
20 Nm ◽  
The Impact ◽  
Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

scholarly journals Monte Carlo Simulation of Non-Local Transport Effects in Strained Si on Relaxed Si1 – xGex Heterostructures

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 253-256
Author(s):  
F. Gámiz ◽  
J. B. Roldán ◽  
J. A. López-Villanueva
Keyword(s):  
Monte Carlo ◽  
Performance Enhancement ◽  
Deep Submicron ◽  
Strained Si ◽  
Electron Transport Properties ◽  
Transport Effects ◽  
Non Local ◽  
Local Transport ◽  
Monte Carlo Simulator ◽  
The Impact

Electron transport properties of strained-Si on relaxed Si1 – xGex channel MOSFETs have been studied using a Monte Carlo simulator. The steady- and non-steady-state high-longitudinal field transport regimes have been described in detail. Electronvelocity- overshoot effects are studied in deep-submicron strained-Si MOSFETs, where they show an improvement over the performance of their normal silicon counterparts. The impact of the Si layer strain on the performance enhancement are described in depth in terms of microscopic magnitudes.

Low Frequency Noise Analysis in Advanced CMOS Devices

2011 ◽  
Vol 324 ◽  
pp. 441-444 ◽  
Author(s):  
Jalal Jomaah ◽  
Majida Fadlallah ◽  
Gerard Ghibaudo
Keyword(s):  
Experimental Data ◽  
Noise Analysis ◽  
Low Frequency ◽  
Deep Submicron ◽  
Electrical Noise ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Noise Sources ◽  
The Impact ◽  
Mobility Fluctuations

A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are illustrated through experimental data obtained on advanced CMOS generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown.

The impact of plasma-charging damage on the RF performance of deep-submicron MOSFET

2002 ◽  
Vol 23 (6) ◽  
pp. 309-311
Author(s):  
L. Pantisano ◽  
K.P. Cheung ◽  
P.J. Roussel ◽  
A. Paccagnella
Keyword(s):  
Deep Submicron ◽  
Rf Performance ◽  
The Impact

scholarly journals Study of Analog/Rf and Stability Investigation of Surrounded Gate Junctionless Graded Channel MOSFET(SJLGC MOSFET)

2021 ◽  
Author(s):  
Sarita Misra ◽  
Sudhansu Mohan Biswal ◽  
Biswajit Baral ◽  
Sanjit Kumar Swain ◽  
Sudhansu Kumar Pati
Keyword(s):  
Drain Current ◽  
Rf Circuits ◽  
Superior Performance ◽  
Threshold Region ◽  
Lateral Direction ◽  
Subthreshold Region ◽  
Digital Switching ◽  
Rf Performance ◽  
The Impact ◽  
Rf Performances

Abstract This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID) , transconductance (gm) ,cut off frequency (fT) , maximum frequency of oscillation (fmax) , critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45%, 29% and 18% respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74% improvement in intrinsic voltage gain (gm / gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.

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