Prediction model for estimating leakage power consumption of routing resources in FPGAs

2011 ◽  
Author(s):  
Behzad Salami ◽  
Morteza Saheb Zamani
Keyword(s):  
Power Consumption ◽  
Prediction Model ◽  
Leakage Power

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

From Chip to Cooling Tower Data Center Modeling: Chip Leakage Power and its Impact on Cooling Infrastructure Energy Efficiency

2011 ◽  
Author(s):  
Thomas J. Breen ◽  
Ed J. Walsh ◽  
Jeff Punch ◽  
Amip J. Shah ◽  
Cullen E. Bash ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Power Consumption ◽  
Data Center ◽  
Heat Dissipation ◽  
Linear Models ◽  
Operating Temperature ◽  
Leakage Power ◽  
Operating Conditions ◽  
Operating Temperatures ◽  
The Impact

The power consumption of the chip package is known to vary with operating temperature, independently of the workload processing power. This variation is commonly known as chip leakage power, typically accounting for ∼10% of total chip power consumption. The influence of operating temperature on leakage power consumption is a major concern for the IT industry for design optimization where IT system power densities are steadily increasing and leakage power expected to account for up to ∼50% of chip power in the near future associated with the reducing package size. Much attention has been placed on developing models of the chip leakage power as a function of package temperature, ranging from simple linear models to complex super-linear models. This knowledge is crucial for IT system designers to improve chip level energy efficiency and minimize heat dissipation. However, this work has been focused on the component level with little thought given to the impact of chip leakage power on entire data center efficiency. Studies on data center power consumption quote IT system heat dissipation as a constant value without accounting for the variance of chip power with operating temperature due to leakage power. Previous modeling techniques have also omitted this temperature dependent relationship. In this paper we discuss the need for chip leakage power to be included in the analysis of holistic data center performance. A chip leakage power model is defined and its implementation into an existing multi-scale data center energy model is discussed. Parametric studies are conducted over a range of system and environment operating conditions to evaluate the impact of varying degrees of chip leakage power. Possible strategies for mitigating the impact of leakage power are also illustrated in this study. This work illustrates that when including chip leakage power in the data center model, a compromise exists between increasing operating temperatures to improve cooling infrastructure efficiency and the increase in heat load at higher operating temperatures due to leakage power.

scholarly journals Short-Term Electricity Consumption Forecasting Based on the EMD-Fbprophet-LSTM Method

2021 ◽  
Vol 2021 ◽  
pp. 1-9
Author(s):  
Guorong Zhu ◽  
Sha Peng ◽  
Yongchang Lao ◽  
Qichao Su ◽  
Qiujie Sun
Keyword(s):  
Time Series ◽  
Power Consumption ◽  
Prediction Model ◽  
Time Series Prediction ◽  
Electricity Consumption ◽  
Operating Efficiency ◽  
Short Term ◽  
Model Based ◽  
Consumption Data ◽  
Consumption Prediction

Short-term electricity consumption data reflects the operating efficiency of grid companies, and accurate forecasting of electricity consumption helps to achieve refined electricity consumption planning and improve transmission and distribution transportation efficiency. In view of the fact that the power consumption data is nonstationary, nonlinear, and greatly influenced by the season, holidays, and other factors, this paper adopts a time-series prediction model based on the EMD-Fbprophet-LSTM method to make short-term power consumption prediction for an enterprise's daily power consumption data. The EMD model was used to decompose the time series into a multisong intrinsic mode function (IMF) and a residual component, and then the Fbprophet method was used to predict the IMF component. The LSTM model is used to predict the short-term electricity consumption, and finally the prediction value of the combined model is measured based on the weights of the single Fbprophet and LSTM models. Compared with the single time-series prediction model, the time-series prediction model based on the EMD-Fbprophet-LSTM method has higher prediction accuracy and can effectively improve the accuracy of short-term regional electricity consumption prediction.

scholarly journals ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS

10.6036/10108 ◽  
2022 ◽  
Vol 97 (1) ◽  
pp. 79-84
Author(s):  
RUBAN GLADWIN ◽  
NEHRU KASTHURI
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Cyber Security ◽  
Energy Recovery ◽  
High Energy ◽  
Leakage Power ◽  
Handheld Devices ◽  
Power Gating ◽  
Hybrid Energy ◽  
Adiabatic Logic

The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

scholarly journals Low Power Checks in Multi Voltage Designs

2020 ◽  
Vol 11 ◽  
pp. 105-111
Author(s):  
K. R. Haripriya ◽  
Ajay Somkuwar ◽  
Laxmi Kumre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Semiconductor Industry ◽  
Power Saving ◽  
Critical Issue ◽  
Leakage Power ◽  
Design Flow ◽  
Power Gating ◽  
Low Power Architectures

Leakage power consumption has been almost a serious problem these days in semiconductor industry. Many low power techniques like multi-voltage, power gating etc. are deployed to improve power saving. Power aware verification hence has become a critical issue now. Static low power verification has been developed to verify that low power architectures are designed in correct approach meeting all electrical rules in SoC. The UPF(Unified Power Format) is the standardized format that has all power intent information and can be used throughout the design flow to ensure that the power specification is intact. Firstly, this paper describes the special cells and its operation used in low power techniques. Secondly it describes the major checks examined at each stage using Synopsys VCLP tool and finally debugging with the tool and conclusion.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

scholarly journals A New Prediction Model for Power Consumption with Local Weather Information

2016 ◽  
Vol 16 (11) ◽  
pp. 488-498
Author(s):  
Haesung Tak ◽  
Taeyong Kim ◽  
Hwan-Gue Cho ◽  
Heeje Kim
Keyword(s):  
Power Consumption ◽  
Prediction Model ◽  
Weather Information ◽  
Local Weather
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