High Performance Germanium n+/p Shallow Junction for nano-Scaled n-MOSFET

ABSTRACTRapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.

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S/D Engineering for Sub-100 nm MOSFET using Ultra Shallow Junction Formation Technique, Elevated S/D Structure and SALICIDE Technique

MRS Proceedings ◽

10.1557/proc-717-c2.2 ◽

2002 ◽

Vol 717 ◽

Cited By ~ 6

Author(s):

Kazuya Ohuchi ◽

Kanna Adachi ◽

Akira Hokazono ◽

Yoshiaki Toyoshima

Keyword(s):

High Performance ◽

Process Integration ◽

Chemical Vapor ◽

Physical Constant ◽

Complementary Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Short Channel ◽

Shallow Junction ◽

Ultrashallow Junctions ◽

Parasitic Resistance

AbstractSuppression of short channel effect (SCE) by utilizing the technology of formation of ultrashallow junctions is one of the important issues. The annealing process of implantation-damage that induces transient enhanced diffusion during a subsequent thermal process, such as low-pressure chemical vapor deposition (LPCVD) for gate sidewall spacer, should be optimized. To pursuit high performance of MOSFETs, parasitic resistance must be reduced with scaling. On the other hand, it is difficult to decrease the parasitic resistance in the region of contact junction, which is a function of physical constant such as Schottky barrier height of silicide materials and solid solubility of dopant. The elevated source/drain structure reduces parasitic resistance of contact junction due to reduction of resistance of diffusion beneath salicide materials. Cobalt salicide is widely used till 100nm node. However, cobalt salicide has disadvantage in the thermal budget for shallow junction and quantity of silicon consumption during silicidation. Nickel salicide is one of the candidates for successor of cobalt salicide to 70 nm node or above, because of its characteristics of low temperature formation, low silicon consumption and low contact resistivity on p+ junctions. In this paper, S/D engineering will be discussed from the viewpoint of the process integration of sub-100 nm physical gate length complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) device.

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Simulation Of Ultra Shallow Junction Formation For Nano Devices Applications By Dopant Diffusion From Spin On Glasses

Jurnal Teknologi ◽

10.11113/jt.v45.336 ◽

2012 ◽

Cited By ~ 3

Author(s):

Nik Hazura N. Hamat ◽

Uda Hashim ◽

Ibrahim Ahmad

Keyword(s):

Sheet Resistance ◽

High Performance ◽

High Surface ◽

Deep Submicron ◽

Short Channel ◽

Shallow Junction ◽

Si Substrates ◽

Junction Formation ◽

Shallow Junctions ◽

Ultra Shallow Junctions

Bagi merealisasikan MOSFET submikron, simpangan cetek ultra berkerintangan rendah diperlukan bagi menghalang kesan saluran pendek dan bagi meningkatkan peranti. Dalam kajian ini, pembentukan simpangan cetek ultra disimulasikan menggunakan perisian ATHENA dan Silvaco Inc. bagi memodelkan resapan dari SOD ke dalam silikon. Simpangan ultra P+N berkualiti tinggi dengan kedalaman 40 nm telah dibentuk menggunakan ciri–ciri yang baik dengan arus bocor serendah 0.5 na/cm2. Simpangan cetek kurang daripada turut diperoleh tetapi kualiti simpangan–simpangan cetek ini kurang baik disebabkan oleh arus bocor permukaan yang tinggi. Pembentukan simpangan dari resapan lapisan polisilikon di atas silikon diikuti oleh SOD di atasnya menghasilkan simpangan yang lebih cetek yang berkerintangan rendah. Kata kunci: Simpangan cetek ultra, resapan, SOD, ATHENA, MOSFET For realizing deep submicron MOSFETs, ultra shallow junctions with low sheet resistance and high doping concentrations are required to suppress short channel effects and to increase the performance. In this paper, ultra shallow junctions were simulated using ATHENA software package from Silvaco TCAD Tools to model the diffusion from spin on dopant (SOD) into silicon. High performance 40 nm P+N shallow junction fabricated by rapid thermal diffusion of B150 into silicon have been obtained. The junction showed very good characteristics with leakage currents as low as 0.5 nA/cm2. Shallow junctions less than 20 nm have also been obtained but the quality was not very good due to very high surface leakage current. Junction formation by diffusion of polysilicon layer on Si substrates then SOD layer deposition on top of it produced shallower junctions with low sheet resistance. Key words: Ultra shallow junction, MOSFET, ULSI, diffusion, spin on dopant, ATHENA, ATLAS

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