Power consumption improvement with residue code for fault tolerance on SRAM FPGA

2011 ◽  
Author(s):  
Amiel Frederic ◽  
Ea Thomas ◽  
Vinay Vashishtha
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Residue Code ◽  
Sram Fpga

PECA

2014 ◽  
pp. 239-248
Author(s):  
Maytham Safar ◽  
Hasan Al-Hamadi ◽  
Dariush Ebrahimi
Keyword(s):  
Wireless Sensor Networks ◽  
Fault Tolerance ◽  
Sensor Networks ◽  
Power Consumption ◽  
Low Power ◽  
The Self ◽  
Wireless Sensor ◽  
Human Intervention ◽  
Electronic Circuits ◽  
Power Efficient

Wireless sensor networks (WSN) have emerged in many applications as a platform to collect data and monitor a specified area with minimal human intervention. The initial deployment of WSN sensors forms a network that consists of randomly distributed devices/nodes in a known space. Advancements have been made in low-power micro-electronic circuits, which have allowed WSN to be a feasible platform for many applications. However, there are two major concerns that govern the efficiency, availability, and functionality of the network—power consumption and fault tolerance. This paper introduces a new algorithm called Power Efficient Cluster Algorithm (PECA). The proposed algorithm reduces the power consumption required to setup the network. This is accomplished by effectively reducing the total number of radio transmission required in the network setup (deployment) phase. As a fault tolerance approach, the algorithm stores information about each node for easier recovery of the network should any node fail. The proposed algorithm is compared with the Self Organizing Sensor (SOS) algorithm; results show that PECA consumes significantly less power than SOS.

PECA

2011 ◽  
Vol 6 (1) ◽  
pp. 49-58 ◽  
Author(s):  
Maytham Safar ◽  
Hasan Al-Hamadi ◽  
Dariush Ebrahimi
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Cluster Algorithm ◽  
The Self ◽  
Wireless Sensor ◽  
Electronic Circuits ◽  
Power Efficient ◽  
Tolerance Approach ◽  
Made In ◽  
Network Power

Wireless sensor networks (WSN) have emerged in many applications as a platform to collect data and monitor a specified area with minimal human intervention. The initial deployment of WSN sensors forms a network that consists of randomly distributed devices/nodes in a known space. Advancements have been made in low-power micro-electronic circuits, which have allowed WSN to be a feasible platform for many applications. However, there are two major concerns that govern the efficiency, availability, and functionality of the network—power consumption and fault tolerance. This paper introduces a new algorithm called Power Efficient Cluster Algorithm (PECA). The proposed algorithm reduces the power consumption required to setup the network. This is accomplished by effectively reducing the total number of radio transmission required in the network setup (deployment) phase. As a fault tolerance approach, the algorithm stores information about each node for easier recovery of the network should any node fail. The proposed algorithm is compared with the Self Organizing Sensor (SOS) algorithm; results show that PECA consumes significantly less power than SOS.

An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant Arithmetic

2019 ◽  
Vol 28 (14) ◽  
pp. 1950244
Author(s):  
Ahmad Towhidy ◽  
Reza Omidi ◽  
Karim Mohammadi
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Design Procedure ◽  
Current Mode ◽  
Vlsi Circuits ◽  
Technology Scaling ◽  
Residue Code ◽  
Logic Unit

Due to technology scaling, reliability has become one of the biggest challenges in VLSI circuits. A number of techniques have been introduced in the literature, especially for arithmetic and logic unit in computers. One of well-known schemes for fault-tolerant arithmetic is the use of arithmetic residue codes. A key problem with most of the previous works regarding residue-based checker is that these methods impose an unacceptable area penalty. In this paper, we propose a novel residue checker with current mode multi-valued logic (CMMVL). A plain design procedure with arbitrary modulo is introduced; also a more efficient integrated scheme for modulo 3 has been demonstrated. The results of the plain CMMVL scheme showed up to 19.5% and 42.9% lower delay and power consumption, respectively, compared with those of the conventional CMOS. Also, utilizing the integrated CMMVL provided, on average, about 17.7% and 80.2% lower delay and power consumption, respectively.

scholarly journals Fault-tolerant architecture for Cache : Summaries, Assessments and Trends

2021 ◽  
Vol 2113 (1) ◽  
pp. 012068
Author(s):  
Xuru Wang ◽  
Xin Gao ◽  
Zongnan Liang ◽  
Jiawei Nian ◽  
Hongjin Liu
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Future Development ◽  
Fault Tolerant ◽  
Development Trend ◽  
The Other ◽  
Architecture Design ◽  
Related Research ◽  
Cache Architecture ◽  
The Future

Abstract Fault-tolerant design of cache is a key aspect of highly reliable processor design. In this paper, based on the key metrics in Cache architecture design: reliability, power consumption, latency and area, we divided the related research into two categories: one is to maximize reliability with guaranteed latency, power consumption and area, the other is to minimize latency, power consumption and area loss while ensuring fault tolerance reliability. Based on the classification, by analyzing different studies of Data and Tag in Cache, this paper gives the characteristics of these methods and the future development trend.

scholarly journals Increasing WSN Lifetime using Clustering and Fault Tolerance Methods

2021 ◽  
Vol 17 (1) ◽  
pp. 1-6
Author(s):  
Sama Sabah ◽  
Muayad Croock
Keyword(s):  
Energy Consumption ◽  
Fault Tolerance ◽  
Power Consumption ◽  
Energy Efficient ◽  
High Energy ◽  
Tolerance Strategy ◽  
Battery Power ◽  
Wsn Lifetime ◽  
Leach Protocol ◽  
Made In

Energy consumption problems in wireless sensor networks are an essential aspect of our days where advances have been made in the sizes of sensors and batteries, which are almost very small to be placed in the patient's body for remote monitoring. These sensors have inadequate resources, such as battery power that is difficult to replace or recharge. Therefore, researchers should be concerned with the area of saving and controlling the quantities of energy consumption by these sensors efficiently to keep it as long as possible and increase its lifetime. In this paper energy-efficient and fault-tolerance strategy is proposed by adopting the fault tolerance technique by using the self-checking process and sleep scheduling mechanism for avoiding the faults that may cause an increase in power consumption as well as energy-efficient at the whole network. this is done by improving the LEACH protocol by adding these proposed strategies to it. Simulation results show that the recommended method has higher efficiency than the LEACH protocol in power consumption also can prolong the network lifetime. In addition, it can detect and recover potential errors that consume high energy.

scholarly journals Técnicas de Tolerância a Falhas em uma Plataforma para Prototipagem Rápida Usando Microcontroladores

2019 ◽  
Author(s):  
Kleber Kruger ◽  
Fabio Iaione
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Rapid Prototyping ◽  
System Performance ◽  
Processing Time ◽  
Fault Tolerant ◽  
Weather Station ◽  
Fault Tolerant System ◽  
Sram Memory

This paper describes the implementation of fault tolerance techniques (based on data and processing redundancy) in programming of a rapid prototyping platform using microcontrollers. To evaluate performance of these techniques was used a fault injector software and a weather station system as a case study. Experiments simulated faults in sensor readings and faults in SRAM memory regions of the weather station. Finally, the fault-tolerant system performance is presented in comparison with non-fault-tolerant system, considering incidence of failures, processing time, memory and power consumption.

Design of a New Parity Preserving Reversible Full Adder

2014 ◽  
Vol 24 (01) ◽  
pp. 1550006 ◽  
Author(s):  
Majid Haghparast ◽  
Soghra Shoaei
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Error Detection ◽  
Power Dissipation ◽  
Vlsi Design ◽  
Full Adder ◽  
Digital Systems ◽  
The Other ◽  
Optimum Number ◽  
Quantum Cost

Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-preserving reversible full adder circuit with a QC of only 9. In addition, the proposed parity-preserving reversible full adder has optimum number of constant inputs and garbage outputs. A novel parity-preserving reversible 4:2 compressor circuit is also proposed using the proposed parity-preserving reversible full adder. This article would be a great initiation for building more complex parity-preserving reversible circuits. All the scales are in the nanometric area, and their fundamental parts are no bigger than a few nanometers.

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