Mechanical tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps

The tensile fracture behavior for solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps was examined. The annealing temperatures were in the range of 125–170 °C for 500 h. Prior to solid state annealing, the eutectic Sn–37Pb (SnPb) and Sn–0.7Cu (SnCu) solders showed fracture through the bulk solder. Brittle interfacial fracture occurred in the Sn–3.5Ag (SnAg) solder. After solid-state annealing, the fracture behavior changed dramatically. For eutectic SnPb solder, the fracture modes gradually changed from cohesive solder failure to interfacial fracture with increasing annealing temperature. The fracture mode of the SnCu solder showed greater change than the SnPb and SnCu solders. After annealing at 125 °C, the SnAg solder had a ductile taffy pull fracture, but an increase in temperature resulted in brittle interfacial fracture again. The SnCu solder maintained the same ductile taffy pull mode up to170 °C annealing, independent of the under bump metallization (UBM) type. Microstructure analysis showed that the interfacial fracture of the SnPb and SnAg solder bumps was ascribed to Pb-rich layer formation and Ag embrittlement at the interface, respectively. The bulk solder fracture of SnAg annealed at 125 °C appeared to be a transient phenomenon due to the abrupt breakdown of the hard lamella structure. The eutectic SnCu solder bumps had no significant change in the interfacial structure, except for interfacial intermetallic growth.

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Growth Kinetics of Reaction Layers in Flip Chip Joints with Cu-cored Lead-free Solder Balls

MATERIALS TRANSACTIONS ◽

10.2320/matertrans.45.754 ◽

2004 ◽

Vol 45 (3) ◽

pp. 754-758 ◽

Cited By ~ 11

Author(s):

Ikuo Shohji ◽

Yuji Shiratori ◽

Hiroshi Yoshida ◽

Masahiko Mizukami ◽

Akira Ichida

Keyword(s):

Growth Kinetics ◽

Flip Chip ◽

Lead Free ◽

Lead Free Solder ◽

Solder Balls ◽

Free Solder ◽

Kinetics Of Reaction ◽

Kinetics Of

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Ultra low-k die crack study for lead free solder bump flip-chip packaging

Journal of Materials Science Materials in Electronics ◽

10.1007/s10854-010-0248-y ◽

2010 ◽

Vol 22 (8) ◽

pp. 988-994 ◽

Cited By ~ 4

Author(s):

K. M. Chen

Keyword(s):

Flip Chip ◽

Solder Bump ◽

Lead Free ◽

Lead Free Solder ◽

Flip Chip Packaging ◽

Free Solder ◽

Low K

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Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids

International Symposium on Microelectronics ◽

10.4071/isom-2017-wa24_104 ◽

2017 ◽

Vol 2017 (1) ◽

pp. 000201-000207 ◽

Cited By ~ 1

Author(s):

Youngtak Lee ◽

Doug Link

Keyword(s):

Hearing Aids ◽

Flip Chip ◽

Failure Modes ◽

Lead Free ◽

Lead Free Solder ◽

Solder Paste ◽

Practical Application ◽

Surface Mount ◽

Free Solder ◽

On Chip

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Considerable amount of defects associated with solder overflow are found on chip-on-flip-chip (COFC) SiP in hearing aids. Through the use of design of experiments (DOE), lead-free solder defect causes on hearing aids application can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components for hearing aid applications. The practical application and analysis of lead-free solder for hearing aids will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types through the DOE process.

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Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

International Symposium on Microelectronics ◽

10.4071/isom-2015-thp25 ◽

2015 ◽

Vol 2015 (1) ◽

pp. 000799-000805

Author(s):

Marek Gorywoda ◽

Rainer Dohle ◽

Bernd Kandler ◽

Bernd Burger

Keyword(s):

Thin Film ◽

High Stability ◽

Flip Chip ◽

Lead Free ◽

Published Data ◽

Organic Substrates ◽

Lead Free Solder ◽

Ceramic Substrates ◽

Solder Bumps ◽

Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

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Comparative Modeling and Analysis of Lead-Free Solder Extrusion for the Design of Reliability

International Symposium on Microelectronics ◽

10.4071/isom-2016-tp53 ◽

2016 ◽

Vol 2016 (1) ◽

pp. 000111-000116

Author(s):

Youngtak Lee ◽

Doug Link

Keyword(s):

Design Of Experiments ◽

Flip Chip ◽

Failure Modes ◽

Form Factors ◽

Lead Free ◽

Lead Free Solder ◽

Solder Paste ◽

Modeling And Analysis ◽

Surface Mount ◽

Free Solder

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Through the use of design of experiments (DOE), lead-free solder defect causes can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components. The systematic investigation will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types utilizing the design of experiments methods.

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Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

International Symposium on Microelectronics ◽

10.4071/isom-2013-tp66 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000420-000423

Author(s):

Kwang-Seong Choi ◽

Ho-Eun Bae ◽

Haksun Lee ◽

Hyun-Cheol Bae ◽

Yong-Sung Eom

Keyword(s):

Screen Printing ◽

Flip Chip ◽

Solder Bump ◽

Low Cost ◽

Organic Substrate ◽

Lead Free ◽

Lead Free Solder ◽

Thermally Activated ◽

Fine Pitch ◽

Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

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