Tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps

2004 ◽  
Vol 19 (6) ◽  
pp. 1826-1834 ◽  
Author(s):  
Jin-Wook Jang ◽  
Ananda P. De Silva ◽  
Jong-Kai Lin ◽  
Darrel R. Frear
Keyword(s):  
Solid State ◽  
Fracture Behavior ◽  
Flip Chip ◽  
Interfacial Fracture ◽  
Bulk Solder ◽  
Tensile Fracture ◽  
Solder Bumps ◽  
Snag Solder ◽  
Free Solder ◽  
Eutectic Snpb

The tensile fracture behavior for solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps was examined. The annealing temperatures were in the range of 125–170 °C for 500 h. Prior to solid state annealing, the eutectic Sn–37Pb (SnPb) and Sn–0.7Cu (SnCu) solders showed fracture through the bulk solder. Brittle interfacial fracture occurred in the Sn–3.5Ag (SnAg) solder. After solid-state annealing, the fracture behavior changed dramatically. For eutectic SnPb solder, the fracture modes gradually changed from cohesive solder failure to interfacial fracture with increasing annealing temperature. The fracture mode of the SnCu solder showed greater change than the SnPb and SnCu solders. After annealing at 125 °C, the SnAg solder had a ductile taffy pull fracture, but an increase in temperature resulted in brittle interfacial fracture again. The SnCu solder maintained the same ductile taffy pull mode up to170 °C annealing, independent of the under bump metallization (UBM) type. Microstructure analysis showed that the interfacial fracture of the SnPb and SnAg solder bumps was ascribed to Pb-rich layer formation and Ag embrittlement at the interface, respectively. The bulk solder fracture of SnAg annealed at 125 °C appeared to be a transient phenomenon due to the abrupt breakdown of the hard lamella structure. The eutectic SnCu solder bumps had no significant change in the interfacial structure, except for interfacial intermetallic growth.

Measurement of electromigration activation energy in eutectic SnPb and SnAg flip-chip solder joints with Cu and Ni under-bump metallization

2010 ◽  
Vol 25 (9) ◽  
pp. 1847-1853 ◽  
Author(s):  
Hsiao-Yun Chen ◽  
Chih Chen
Keyword(s):  
Activation Energy ◽  
Flip Chip ◽  
Void Formation ◽  
Under Bump Metallization ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Snag Solder ◽  
Temperature Coefficient Of Resistivity ◽  
Eutectic Snpb ◽  
Real Temperature

Electromigration activation energy is measured by a built-in sensor that detects the real temperature during current stressing. Activation energy can be accurately determined by calibrating the temperature using the temperature coefficient of resistivity of an Al trace. The activation energies for eutectic SnAg and SnPb solder bumps are measured on Cu under-bump metallization (UBM) as 1.06 and 0.87 eV, respectively. The activation energy mainly depends on the formation of Cu–Sn intermetallic compounds. On the other hand, the activation energy for eutectic SnAg solder bumps with Cu–Ni UBM is measured as 0.84 eV, which is mainly related to void formation in the solder.

Sub-100 μm SnAg Solder Bumping Technology and the Bump Reliability

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Xiaoqin Lin ◽  
Le Luo
Keyword(s):  
Cu6sn5 Phase ◽  
X Ray ◽  
Solder Bumps ◽  
Average Shear Strength ◽  
Average Shear ◽  
Snag Solder ◽  
Packaging Industry ◽  
Negative Impacts ◽  
Free Solder ◽  
Electroplating Process

Lead-free solder bumping and its related interconnection and reliability are becoming one of the important issues in today’s electronic packaging industry. In this paper, alloy electroplating was used as SnAg solder bumping process. Multiple reflow was preformed on as-plated solder bumps. Scanning electron microscopy and energy dispersive X-ray analysis were used to investigate the intermetallic compound and microvoids of cross-sectioned solder bump. Shear test was used to evaluate the reliabilities of the SnAg bumps. The 13×13 area-array Sn/3.0Ag solder bumps of 70 μm in height and 90 μm in diameter were fabricated with a smooth and shiny surface and with a uniform distribution of Ag. During multireflow, the scalloped Cu6Sn5 phase grows by a ripening process. Volume shrinkage was the main reason for the formation of microvoids during multireflow. The average shear strength of solder bumps on TiW/Cu under bump metallurgy (UBM) increased with reflow times. The electroplating process is suitable for mass production of well-controlled geometry and uniformity of SnAg solder bumps. Microvoids have trivial negative impacts on the solder bonds. The combination of TiW/Cu UBM and SnAg solder is reliable.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

40 μm Copper–Silver Composite Flip-Chip Interconnect Technology Using Solid-State Bonding

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Chu-Hsuan Sha ◽  
Wen P. Lin ◽  
Chin C. Lee
Keyword(s):  
Solid State ◽  
Flip Chip ◽  
Thermal Expansion Mismatch ◽  
Conduction Electrons ◽  
Solid State Bonding ◽  
Cu Substrates ◽  
Atomic Distance ◽  
Free Solder ◽  
Interconnect Technology ◽  
Silver Composite

Copper–silver (Cu–Ag) composite flip-chip interconnect between silicon (Si) chips and Cu substrates is demonstrated. Array of Cu–Ag columns, each 28 μm in height and 40 μm in diameter, is electroplated on 2-in. Si wafers coated with chromium (Cr)/gold (Au) dual layer. The Si wafers are diced into 6 mm × 6 mm chips, each containing 50 × 50 Cu–Ag columns. The Si chip with Cu–Ag columns is bonded to Cu substrates at 260 °C in 80 mTorr vacuum. A bonding force of only 1.8 kg is applied, corresponding to 0.71 g per Cu–Ag column. During bonding, Ag atoms in Cu–Ag columns deform and their surfaces conform to and mate with the surface of Cu substrate. Solid-state bonding incurs when Ag atoms in Cu–Ag columns and Cu atoms in Cu substrates are brought within atomic distance so that they share conduction electrons. The Cu–Ag columns are indeed bonded to the Cu. No molten phase is involved in the bonding. The joint consists of 60% Cu section and 40% Ag section. The ductile Ag is able to accommodate the thermal expansion mismatch between Si and Cu. The Cu–Ag joints do not contain any intermetallic compound (IMC). This interconnect technology avoids all reliability issues associated with IMC growth in conventional soldering processes. Compared to tin-based lead-free solder joints, Cu–Ag composite joints have superior electrical and thermal properties.

Lead-Free and PbSn Bump Electromigration Testing

2005 ◽  
Author(s):  
Stephen Gee ◽  
Nikhil Kelkar ◽  
Joanne Huang ◽  
King-Ning Tu
Keyword(s):  
Cross Sections ◽  
Current Density ◽  
Critical Issue ◽  
Electronics Industry ◽  
Limiting Factor ◽  
Time To Failure ◽  
Solder Bumps ◽  
Free Solder ◽  
Mean Time ◽  
Eutectic Snpb

As the electronics industry continues to push for miniaturization, several reliability factors become vital issues. The demand for a high population of smaller and smaller solder bumps, while also increasing the current, have resulted in a significant increase in the current density. As outlined in the International Technology of Roadmap for Semiconductors (ITRS), this trend makes electromigration the limiting factor in high density packages. The heightened current density and correspondingly elevated operating temperatures are a critical issue in reliability since these factors facilitate the effects of electromigration. Therefore, as bump sizes continue to decrease, the study of electromigration reliability becomes crucial in order to understand and possibly prevent the causes of failure. A systematic study of electromigration in eutectic SnPb and Pb-free solder bumps was conducted in order to characterize the reliability of the Micro SMD package family. The testing includes both eutectic 63Sn-37Pb and 95.5Sn4.0Ag-0.5Cu solder bumps on an Al/Ni(V)/Cu under-bump-metallization. Mean-time-to-failure results are compared to Black’s Equation and cross-sections of the solder bumps are shown to analyze the mechanisms that led to failure.

scholarly journals Cross interactions on interfacial compound formation of solder bumps and metallization layers during reflow

2004 ◽  
Vol 19 (12) ◽  
pp. 3654-3664 ◽  
Author(s):  
T.L. Shao ◽  
T.S. Chen ◽  
Y.M. Huang ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Driving Forces ◽  
The Other ◽  
Compound Formation ◽  
Bump Height ◽  
Performance Requirements ◽  
Substrate Side ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Eutectic Snpb

While the dimension of solder bumps keeps shrinking to meet higher performance requirements, the formation of interfacial compounds may be affected more profoundly by the other side of metallization layer due to a smaller bump height. In this study, cross interactions on the formation of intermetallic compounds (IMCs) were investigated in eutectic SnPb, SnAg3.5, SnAg3.8Cu0.7, and SnSb5 solders jointed to Cu/Cr–Cu/Ti on the chip side and Au/Ni metallization on the substrate side. It is found that the Cu atoms on the chip side diffused to the substrate side to form (Cux,Ni1−x)6Sn5 or (Niy,Cu1−y)3Sn4 for the four solders during the reflow for joining flip chip packages. For the SnPb solder, Au atoms were observed on the chip side after the reflow, yet few Ni atoms were detected on the chip side. In addition, for SnAg3.5 and SnSn5 solders, the Ni atoms on the substrate side migrated to the chip side during the reflow to change binary Cu6Sn5 into ternary (Cux,Ni1−x)6Sn5 IMCs, in which the Ni weighed approximately 21%. Furthermore, it is intriguing that no Ni atoms were detected on the chip side of the SnAg3.8Cu0.7 joint. The possible driving forces responsible for the diffusion of Au, Ni, and Cu atoms are discussed in this paper.

Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2004 ◽  
Vol 126 (3) ◽  
pp. 359-366 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Aging Process ◽  
Flip Chip ◽  
Initial Period ◽  
Bulk Solder ◽  
The Body ◽  
Nano Indentation ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine pitch flip chip assembly processes. The solder bumps and joints that were aged at either 80 °C or 150 °C for up to 440 hours (∼18 days); have been studied by an analysis using micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼50 hours) as compared to the non-aged bumps, but a decrease after longer aging (e.g. 440 hours). A brittle Ag3Sn phase formed as large stick-like features in the body of bulk solder and near the interface of solder/UBM during the initial aging, and is attributed with the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the body of solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a large lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process at 150 °C. These are believed to be detrimental to joint reliability.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

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