15μm Silver flip-chip technology with solid-state bonding

2011 ◽  
Author(s):  
Chu-Hsuan Sha ◽  
Chin C. Lee
Keyword(s):  
Solid State ◽  
Flip Chip ◽  
Solid State Bonding ◽  
Chip Technology

Silver Flip-Chip Technology by Solid-State Bonding

2010 ◽  
Vol 132 (3) ◽  
Author(s):  
Pin J. Wang ◽  
Chin C. Lee
Keyword(s):  
Solid State ◽  
Flip Chip ◽  
New Technology ◽  
Bonding Process ◽  
Cu Substrate ◽  
Solid State Bonding ◽  
Chip Technology ◽  
Cu Substrates ◽  
One Step ◽  
Lead Free Solders

Silver flip-chip joints between silicon (Si) chips and copper (Cu) substrates were fabricated using a solid-state bonding process without any solder and without flux. The bonding process was performed at 250°C, compatible with typical reflow temperature for lead-free solders. During the bonding process, there was no molten phase involved. The Ag joints fabricated consisted of only pure Ag without any intermetallic compound (IMC). Thus, reliability issues associated with IMCs and IMC growth do not exist anymore. Silver has the highest electrical conductivity and highest thermal conductivity among all metals. It is also quite ductile and able to deform to release stresses caused by thermal expansion mismatch. Flip-chip joints of high aspect ratio can be accomplished because the joints stay in a solid state during the bonding process. It looks like that silver is the ultimate joining material for flip-chip as well as through-Si-via interconnect technologies. In this study, the solid-state bonding process was first developed using a pure Ag foil to bond a Si chip to a Cu substrate in one step. The bonding strength on two interfaces, Si/Ag and Ag/Cu, passes the MIL-STD-883G Method 2019.7. To demonstrate Ag flip-chip interconnects, Si chips were electroplated with Ag bumps, followed by the solid-state bonding process on Cu substrates. The flip-chip bumps are well bonded to the Cu substrate. It would take some time for this new technology to be probably accepted and utilized in production. On the other hand, the preliminary results in this study show that Ag flip-chip joints can indeed be fabricated at 250°C.

40 μm Copper–Silver Composite Flip-Chip Interconnect Technology Using Solid-State Bonding

2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Chu-Hsuan Sha ◽  
Wen P. Lin ◽  
Chin C. Lee
Keyword(s):  
Solid State ◽  
Flip Chip ◽  
Thermal Expansion Mismatch ◽  
Conduction Electrons ◽  
Solid State Bonding ◽  
Cu Substrates ◽  
Atomic Distance ◽  
Free Solder ◽  
Interconnect Technology ◽  
Silver Composite

Copper–silver (Cu–Ag) composite flip-chip interconnect between silicon (Si) chips and Cu substrates is demonstrated. Array of Cu–Ag columns, each 28 μm in height and 40 μm in diameter, is electroplated on 2-in. Si wafers coated with chromium (Cr)/gold (Au) dual layer. The Si wafers are diced into 6 mm × 6 mm chips, each containing 50 × 50 Cu–Ag columns. The Si chip with Cu–Ag columns is bonded to Cu substrates at 260 °C in 80 mTorr vacuum. A bonding force of only 1.8 kg is applied, corresponding to 0.71 g per Cu–Ag column. During bonding, Ag atoms in Cu–Ag columns deform and their surfaces conform to and mate with the surface of Cu substrate. Solid-state bonding incurs when Ag atoms in Cu–Ag columns and Cu atoms in Cu substrates are brought within atomic distance so that they share conduction electrons. The Cu–Ag columns are indeed bonded to the Cu. No molten phase is involved in the bonding. The joint consists of 60% Cu section and 40% Ag section. The ductile Ag is able to accommodate the thermal expansion mismatch between Si and Cu. The Cu–Ag joints do not contain any intermetallic compound (IMC). This interconnect technology avoids all reliability issues associated with IMC growth in conventional soldering processes. Compared to tin-based lead-free solder joints, Cu–Ag composite joints have superior electrical and thermal properties.

40 μm Ag/Au Flip-Chip Joints by Solid-State Bonding at 200°C

2013 ◽  
Vol 10 (3) ◽  
pp. 120-127
Author(s):  
Wen P. Lin ◽  
Chu-Hsuan Sha ◽  
Chin C. Lee
Keyword(s):  
Solid State ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bonding Interface ◽  
Breaking Force ◽  
Sem Images ◽  
Cross Sectional ◽  
Cu Substrate ◽  
Solid State Bonding ◽  
State Process

In this research, 40 μm silver/gold (Ag/Au) composite flip-chip interconnect joints between silicon (Si) chips and copper (Cu) substrates were demonstrated. The bonding was achieved by a solid-state process at a low temperature of 200°C for 5 min with the pressure applied at 250–400 psi (1.7–2.7 MPa), corresponding to 0.22–0.35 g of force per joint. To begin with, an array of 50 × 50 30 μm Ag/10 μm Au columns with 40 μm in diameter and 100 μm in pitch was fabricated by photolitho-graphic and electroplating processes on silicon (Si) chips which were first coated with chromium (Cr) and Au films. The columns on the chip were then bonded to a Cu substrate by solid-state bonding. Cross-sectional scanning electron microscopy (SEM) images show that the exposed Ag/Au columns were well bonded to the Cu substrate. No joint breakage was observed despite the large coefficient of thermal expansion (CTE) mismatch between Si and Cu. A pull test was conducted. The breaking force and fracture strength are 6.5–7.3 kg and 2,940–3,310 psi (20.2–22.8 MPa), respectively. The breaking force is 2.5× of the criterion specified in MIL-STD-883E. Fracture modes were examined. Three modes were classified by fracture interfaces as Si-glue, Si/Cr/Au/Ag, and Au-Cu bonding interface. Of all joints evaluated, 27% of them break on the Au-Cu substrate bonding interface. Accordingly, the bonding interface is least likely to break among interfaces of the joint structure.

Solid/solid interfacial reactions between Sn–0.7 wt% Cu and Ni–7 wt% V

2008 ◽  
Vol 23 (7) ◽  
pp. 1895-1901 ◽  
Author(s):  
Chih-chi Chen ◽  
Sinn-wen Chen ◽  
Chih-horng Chang
Keyword(s):  
Reaction Time ◽  
Solid State ◽  
Barrier Layer ◽  
Direct Contact ◽  
Flip Chip ◽  
Cu Alloy ◽  
Chip Technology ◽  
Diffusion Barrier Layer ◽  
Free Solder ◽  
State Amorphization

Sn–0.7 wt% Cu alloy is an important Pb-free solder, and Ni–7 wt% V is the major diffusion barrier layer material of flip chip technology. Reactions at the Sn–0.7 wt% Cu/Ni–7 wt% V interface are examined at 160, 180, and 210 °C. Only the Cu6Sn5 phase is formed in the Sn–0.7 wt% Cu/Ni–7 wt% V couple reacted at 160 and 180 °C; however, in addition to the Cu6Sn5 and Ni3Sn4 phases, a quaternary Q phase is formed in the Sn–0.7 wt% Cu/Ni–7 wt% V couple reacted at 210 °C. The Q phase is a mixture of nanocrystalline Ni3Sn4 phase and an amorphous phase. With longer reaction time at 210 °C in the Ni–V/Q/Sn–Cu couple where the Q phase is in direct contact with solder, the Ni3Sn4 phase nucleates inside the preformed Q phase, and the alternating layer phenomenon Ni–V/Q/Ni3Sn4/Q/Ni3Sn4/Cu6Sn5/Sn–Cu is observed. The interesting solid state amorphization and alternating layer phenomena at 210 °C are primarily caused by the fact that Sn and Cu are fast diffusing species, while V is relatively immobile.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Fe/Ni diffusion behavior in the shear-extrusion solid state bonding process

2021 ◽  
Vol 67 ◽  
pp. 35-45
Author(s):  
Shuangjie Zhang ◽  
Wei Wang ◽  
Shibo Ma ◽  
Qiang Li
Keyword(s):  
Solid State ◽  
Bonding Process ◽  
Diffusion Behavior ◽  
Solid State Bonding
Sign in / Sign up

Export Citation Format

Share Document