The Effect of the SnAg Solder Joint Morphology on the Thermal Cycle Reliability of 40 µm Fine-Pitch Cu-Pillar/SnAg Micro Bump Interconnection

2018 ◽  
Author(s):  
SeYong Lee ◽  
HanMin Lee ◽  
JongHo Park ◽  
SangMyung Shin ◽  
WooJeong Kim ◽  
...  
Keyword(s):  
Solder Joint ◽  
Thermal Cycle ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Snag Solder ◽  
Joint Morphology

Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA

2014 ◽  
Author(s):  
Bob Wettermann
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Joint Strength ◽  
Semiconductor Devices ◽  
X Ray ◽  
Fine Pitch ◽  
Manual Methods

Abstract As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.

The Shape Control Process of a Cu/SnAg Solder Joint with a Ni insertion Using Thermo-Compression Bonding

2021 ◽  
Author(s):  
Mingang Fang ◽  
Zhuo Chen ◽  
Fuliang Wang ◽  
Chu Tang ◽  
Wenhui Zhu
Keyword(s):  
Solder Joint ◽  
Shape Control ◽  
Control Process ◽  
Snag Solder

Fine pitch Cu pillar wafer process development and seed layer etching characterization

2012 ◽  
Author(s):  
Li Yan Siow ◽  
Wei Deng ◽  
Qing Xin Zhang ◽  
Tai Chong Chai ◽  
Chee Guan Koh ◽  
...  
Keyword(s):  
Seed Layer ◽  
Process Development ◽  
Cu Pillar ◽  
Fine Pitch

Si Photonics Deployment Using Cu Pillar Interconnect and Chip On Wafer Platform

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001663-001681
Author(s):  
Miguel Jimarez
Keyword(s):  
Light Source ◽  
Silicon Photonics ◽  
High Speed ◽  
High Sensitivity ◽  
Optical Path ◽  
Clock Recovery ◽  
Wafer Scale ◽  
Si Photonics ◽  
Cu Pillar ◽  
Fine Pitch

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.

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