Fine pitch Cu pillar wafer process development and seed layer etching characterization

2012 ◽  
Author(s):  
Li Yan Siow ◽  
Wei Deng ◽  
Qing Xin Zhang ◽  
Tai Chong Chai ◽  
Chee Guan Koh ◽  
...  
Keyword(s):  
Seed Layer ◽  
Process Development ◽  
Cu Pillar ◽  
Fine Pitch

The Novel TEM Sample Preparation Approach for Targeted via with Barrier/Cu Seed Layer Inspection

2009 ◽  
Author(s):  
Wen-Fei Hsieh ◽  
Shih-Hsiang Tseng ◽  
Bo Min She
Keyword(s):  
Sample Preparation ◽  
Cross Section ◽  
Seed Layer ◽  
Target Location ◽  
Process Development ◽  
Process Integration ◽  
Ion Beam ◽  
Main Tool ◽  
Dual Beam ◽  
Sample Preparation Procedure

Abstract In this study, an FIB-based cross section TEM sample preparation procedure for targeted via with barrier/Cu seed layer is introduced. The dual beam FIB with electron beam for target location and Ga ion beam for sample milling is the main tool for the targeted via with barrier/Cu seed layer inspection. With the help of the FIB operation and epoxy layer protection, ta cross section TEM sample at a targeted via with barrier/Cu seed layer could be made. Subsequent TEM inspection is used to verify the quality of the structure. This approach was used in the Cu process integration performance monitor. All these TEM results are very helpful in process development and yield improvement.

Advanced barrier and seed layer deposition enabling multiple type of TSVs integration

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000077-000103
Author(s):  
Thierry Mourier ◽  
Mathilde Gottardi ◽  
Pierre-Emile Philip ◽  
Sophie Verrun ◽  
Gilles Romero ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
Seed Layer ◽  
Process Development ◽  
High Density ◽  
Process Equipment ◽  
Integration Schemes ◽  
Step Coverage ◽  
Wide Range ◽  
Silicon Thickness ◽  
Very High

TSV integration is a key technology allowing heterogeneous devices 3D integration. However, depending on the targeted application, various TSV sizes and integration schemes exist, all requesting very high aspect ratio. The most common integration is the Mid-process TSV for which aspect ratio is required to be higher than 10:1 whatever application. In the case of large interposers, silicon thickness has to be increased to limit the deformation of the substrate due to highly stressed devices. Same requirements are made by photonic interposers which use thick SOI substrate leading to high warpage during integration. In the opposite, imagers requires to save silicon surface thus reduce TSV size and keep out zone. Silicon thickness has to be kept in the 100 μm range leading then the aspect ratio of the TSV to increase. Recently, Hybrid bonding progresses allowed a new type of TSV to be introduced : High Density TSVs for imagers. In this application, micrometer range TSV have to be filled with a Silicon thickness reduction limited to 10 μm by grinding process control. In order to allow the metal filling of all those type of structures, we have developed a highly conformal barrier and seed layer processes using standard materials for easier integration. The process is based on the use of MOCVD TiN as a barrier. This material is deposited using TDMAT precursor which allows low temperature deposition (200 °C)[1] which extends also the polyvalence of the process toward polymer bonded integrations. The very high step coverage of this process, reported at more than 30% in 20:1 aspect ratio coupled to high resistance to copper diffusion allows as thin as 20 nm barrier thickness which appears relevant economically (for deposition and CMP) and for stress consideration, compared to the well known but thicker PVD TaN process. Considering seed layer, the eG3D process[2] was brought to a high maturity allowing it to be integrated in an applied material raider tool coupled to TSV filling reactors. This process, based on electrografting of copper has already proved a step coverage of more than 50% in 12:1 aspect ratio structures. The presented work shows that the same process requires only deposition parameters change to be able to fully cover 10×150 μm Mid-process TSV as well as 1×10 μm High density ones. The excellent step coverage of this process allowed as thin as 200 nm (for 10×120 μm TSVs) and 100 nm (for (1×10 μm ones) deposited thicknesses to ensure perfect coverage of the structures. eG3D process also has the ability to be used as a repair process for non-continuous widely used PVD Cu seed layers but also be deposited directly on the barrier material. These 2 layers were evaluated together in a 300mm TSV integration schemes of both 10×120 mid process and 1×10 μm High Density structures and qualified electrically. The paper will discuss the deposition process development leading to simultaneously allow copper filling of the very wide range of TSVs on the same process equipment and using the same chemicals. We will then present integration results as well as electrical test of TSV daisy chains of both mid and High density TSVs showing excellent yield for all TSV size and integration schemes.

Si Photonics Deployment Using Cu Pillar Interconnect and Chip On Wafer Platform

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001663-001681
Author(s):  
Miguel Jimarez
Keyword(s):  
Light Source ◽  
Silicon Photonics ◽  
High Speed ◽  
High Sensitivity ◽  
Optical Path ◽  
Clock Recovery ◽  
Wafer Scale ◽  
Si Photonics ◽  
Cu Pillar ◽  
Fine Pitch

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

2012 ◽  
Vol 2012 (1) ◽  
pp. 000455-000463 ◽  
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Flip Chip ◽  
Organic Substrate ◽  
Stress Tests ◽  
Cross Sectional ◽  
Current Stress ◽  
Barrier Layers ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Cu Dissolution

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

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