The Effect of the Thermal Mechanical Properties of Nonconductive Films on the Thermal Cycle Reliability of 40-<inline-formula> 
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                  </inline-formula>m Fine Pitch Cu-Pillar/Ni/SnAg Microbump Flip-Chip Assembly

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

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Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

International Symposium on Microelectronics ◽

10.4071/isom-2012-tp61 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000455-000463 ◽

Cited By ~ 2

Author(s):

Yasumitsu Orii ◽

Kazushige Toriyama ◽

Sayuri Kohara ◽

Hirokazu Noma ◽

Keishi Okamoto ◽

...

Keyword(s):

Flip Chip ◽

Organic Substrate ◽

Stress Tests ◽

Cross Sectional ◽

Current Stress ◽

Barrier Layers ◽

Cu Pillar ◽

Fine Pitch ◽

Cu Pillar Bump ◽

Cu Dissolution

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

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Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

International Symposium on Microelectronics ◽

10.4071/isom-2011-wp5-paper4 ◽

2011 ◽

Vol 2011 (1) ◽

pp. 000828-000836

Author(s):

Yasumitsu Orii ◽

Kazushige Toriyama ◽

Sayuri Kohara ◽

Hirokazu Noma ◽

Keishi Okamoto ◽

...

Keyword(s):

Aging Process ◽

Flip Chip ◽

Fem Simulation ◽

Organic Substrate ◽

Organic Substrates ◽

Cross Sectional ◽

Pillar Height ◽

Cu Pillar ◽

Fine Pitch ◽

Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

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Enabling Cu Pillar Flip Chip Assembly with Water Soluble Lead-free Solder Paste

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc47984.2019.9026676 ◽

2019 ◽

Author(s):

B. Senthil Kumar ◽

Bayaras Abito Danila ◽

Chong Mei Hoe Joanne ◽

Zhang Rui Fen ◽

Santosh Kumar Rath ◽

...

Keyword(s):

Flip Chip ◽

Water Soluble ◽

Lead Free ◽

Lead Free Solder ◽

Solder Paste ◽

Cu Pillar ◽

Flip Chip Assembly ◽

Free Solder

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Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for Low Cost and High Performance Flip Chip Package

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2017.216 ◽

2017 ◽

Author(s):

Nokibul Islam ◽

Vinayak Pandey ◽

KyungOe Kim

Keyword(s):

High Performance ◽

Flip Chip ◽

Low Cost ◽

Cu Pillar ◽

Fine Pitch

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Cu Pillar Bumping Technology with Solder Alloy Versatility

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-tha31 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 002360-002376

Author(s):

Guy Burgess ◽

Anthony Curtis ◽

Tom Nilsson ◽

Gene Stout ◽

Theodore G. Tessier

Keyword(s):

Solder Alloy ◽

Flip Chip ◽

Semiconductor Industry ◽

Solder Paste ◽

Cu Pillar ◽

Fine Pitch ◽

Cu Pillar Bump ◽

Wide Range ◽

Method Of Production ◽

Board Level

There is considerable interest in the semiconductor industry regarding Cu pillar bumping for finer pitch flip chip and 3D packaging applications. A common Cu Pillar method of production incorporates a combined Cu plated post topped with a plated solder pillar cap, usually of a Sn or SnAg alloy. Compared with this, a unique method of Cu pillar bump production developed at FlipChip International, LLC (FCI) creates the solder cap by applying and reflowing a solder paste on top of the plated Cu post. This method of production offers several benefits; the most important include a broader solder alloy selection, better alloy control, and improved overall pillar height uniformity. FCI has qualified a wide range of Cu pillar bump sizes, heights and shapes including Cu pillar bumps for fine pitch applications as low as 35um pitch (NANOPillarTM). FCI's Cu pillar bump structures in overmolded SiP have passed JEDEC 22-A104C board level thermal cycle testing, JEDEC J-STD-20A MLS 3@260C, as well as other board level corrosion and shock testing. FCI has demonstrated capping Cu pillar bumps with a broad range of solder alloys tailored to specific application requirements.

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