CMOS 90 nm multi-bias transistor model Up to 66 GHz

Author(s):  
Yunqiu Wu ◽  
Shili Cong ◽  
Chenxi Zhao ◽  
Huihua Liu ◽  
Kai Kang
Keyword(s):  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.


Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 541
Author(s):  
Muhammad Imran Khan ◽  
Ahmed S. Alshammari ◽  
Badr M. Alshammari ◽  
Ahmed A. Alzamil

This work deals with the analysis of spectrum generation from advanced integrated circuits in order to better understand how to suppress the generation of high harmonics, especially in a given frequency band, to design and implement noise-free systems. At higher frequencies, the spectral components of signals with sharp edges contain more energy. However, current closed-form expressions have become increasingly unwieldy to compute higher-order harmonics. The study of spectrum generation provides an insight into suppressing higher-order harmonics (10th order and above), especially in a given frequency band. In this work, we discussed the influence of transistor model quality and input signal on estimates of the harmonic contents of switching waveforms. Accurate estimates of harmonic contents are essential in the design of highly integrated micro- and nanoelectromechanical systems. This paper provides a comparative analysis of various flip-flop/latch topologies on different process technologies, i.e., 130 and 65 nm. An FFT plot of the simulated results signifies that the steeper the spectrum roll-off, the lesser the content of higher-order harmonics. Furthermore, the results of the comparison illustrate the improvement in the rise time, fall time, clock-Q delay and spectrum roll-off on the better selection of slow-changing input signals and more accurate transistor models.


2019 ◽  
Vol 34 (9) ◽  
pp. 9131-9145 ◽  
Author(s):  
Achim Endruschat ◽  
Christian Novak ◽  
Holger Gerstner ◽  
Thomas Heckel ◽  
Christopher Joffe ◽  
...  

2019 ◽  
Vol 66 (1) ◽  
pp. 60-65 ◽  
Author(s):  
Theodor Hillebrand ◽  
Steffen Paul ◽  
Dagmar Peters-Drolshagen

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