The Impact of High-voltage Drift N-well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETs

2007 ◽  
Author(s):  
C. T. Huang ◽  
Bing-Yue Tsui ◽  
Hsu-Ju Liu ◽  
Geeng-Lih Lin
Keyword(s):  
High Voltage ◽  
Electrical Characteristics ◽  
Shallow Trench Isolation ◽  
Voltage Drift ◽  
Trench Isolation ◽  
The Impact

The Impact of Shallow Trench Isolation on the Channel Hot Electron Programming Behaviors of SONOS Cells

2019 ◽  
Vol 18 (1) ◽  
pp. 43-48 ◽  
Author(s):  
Zhiguo Li ◽  
Fan Yang ◽  
Joshua Wang ◽  
Peter Lin ◽  
Jianguang Chang ◽  
...  
Keyword(s):  
Hot Electron ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
The Impact

Numerical Study on SEU Performance of Strain Engineered 6T-SRAM Cells

2021 ◽  
pp. 2250034
Author(s):  
N. Vinodhkumar ◽  
G. Durga ◽  
S. Muthumanickam
Keyword(s):  
Field Effect Transistor ◽  
Numerical Study ◽  
Metal Oxide Semiconductor ◽  
Soft Error ◽  
Oxide Semiconductor ◽  
Error Performance ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Effect Transistor ◽  
The Impact

In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

2007 ◽  
Vol 124-126 ◽  
pp. 29-32
Author(s):  
Nam Hoon Kim ◽  
Hae Young Yoo ◽  
Eui Goo Chang
Keyword(s):  
Flash Memory ◽  
Chemical Mechanical Polishing ◽  
Gate Oxide ◽  
Mechanical Polishing ◽  
The Other ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Dry Oxidation ◽  
The Impact ◽  
Embedded Flash

The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

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