scholarly journals The impact of shallow trench isolation effects on circuit performance

Author(s):  
Sravan K. Marella ◽  
Sachin S. Sapatnekar
2019 ◽  
Vol 18 (1) ◽  
pp. 43-48 ◽  
Author(s):  
Zhiguo Li ◽  
Fan Yang ◽  
Joshua Wang ◽  
Peter Lin ◽  
Jianguang Chang ◽  
...  

Author(s):  
N. Vinodhkumar ◽  
G. Durga ◽  
S. Muthumanickam

In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.


2007 ◽  
Vol 124-126 ◽  
pp. 29-32
Author(s):  
Nam Hoon Kim ◽  
Hae Young Yoo ◽  
Eui Goo Chang

The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.


1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.


MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.


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